Methods and systems for adaptive receiver equalization

• US 7,286,597 B2
• Filed: 04/30/2001
• Issued: 10/23/2007
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wang, Hui, Baumer, Howard A., Jiang, Xicheng, Madisetti, Avanindra, Buchwald, Aaron
• Primary Examiner(s): Fan; Chieh M.
• Assistant Examiner(s): PUENTE, EVA YI ZHENG
• Application Number:
  US09/844,283
• Publication Number:
  US 20020034222A1
• Time in Patent Office: 2,367 Days
• Field of Search: 375/232, 375/229, 375/222, 375/346, 398/82, 704/200, 360/51
• US Class Current: 375/232
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0274 with Costas loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Claims

1. A method for adaptively equalizing a multi-gigabit analog information signal for a signal path, comprising the steps of:

(1) sampling a multi-gigabit analog information signal, thereby generating analog samples;

(2) performing an equalizing process on the analog samples, wherein the equalizing includes minimizing differences between an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples; and

(3) quantizing the equalized analog samples of the multi-gigabit analog information signal.

2. The method according to claim 1, wherein step (2) comprises the steps of:

(a) comparing a multi-level representation of the equalized samples with the quantized equalized samples;

(b) performing a least-means-squared operation on results of the comparison;

(c) adjusting an equalization coefficient with a result of the least-means-squared operation; and

(d) repeating steps (2)(a) through (2)(c).

3. The method according to claim 2, wherein steps (2)(a) through (2)(d) are performed at a sub-sample rate relative to the sampling of step (1).

4. The method according to claim 2, wherein steps (2)(a) through (2)(d) are performed at an off-set of a sub-sample rate relative to the sampling of step (1).

5. The method according to claim 1, wherein step (2) comprises the steps of:

(a) distinguishing between post-transition samples and steady-state samples;

(b) integrating post-transition sample amplitudes;

(c) integrating steady-state sample amplitudes;

(d) determining a difference between the integrated post-transition sample amplitudes and the integrated steady-state sample amplitudes;

(e) adjusting an equalization coefficient to minimize the differences between an average of the integrated post-transition sample amplitudes and an average of the integrated steady-state sample amplitudes; and

(f) repeating steps (2)(a) through (2)(e).

6. The method according to claim 5, wherein steps (2)(a) through (2)(f) are performed at a sub-sample rate relative to the sampling of step (1).

7. The method according to claim 5, wherein steps (2)(a) through (2)(f) are performed at an off-set of a sub-sample rate relative to the sampling of step (1).

8. The method according to claim 1, wherein step (2) comprises the steps of:

(a) distinguishing between post-transition samples and steady-state samples;

(b) averaging post-transition sample amplitudes;

(c) averaging steady-state sample amplitudes;

(d) determining a difference between the averaged post-transition sample amplitudes and the averaged steady-state sample amplitudes;

(e) adjusting an equalization coefficient to minimize the differences between the integrated post-transition sample amplitudes and the integrated steady-state sample amplitudes; and

(f) repeating steps (2)(a) through (2)(e).

9. The method according to claim 1, wherein step (2) comprises the steps of:

(a) distinguishing between post-transition samples and steady-state samples;

(b) accumulating post-transition sample amplitudes;

(c) accumulating steady-state sample amplitudes;

(d) determining a difference between the accumulated post-transition sample amplitudes and the accumulated steady-state sample amplitudes;

(e) adjusting an equalization coefficient to minimize the differences between an average of the integrated post-transition sample amplitudes and an average of the integrated steady-state sample amplitudes; and

(f) repeating steps (2)(a) through (2)(e).

10. The method according to claim 1, wherein step (2) comprises the step of minimizing inter-symbol interferences in the samples.

11. A method for adaptively equalizing time staggered portions of a multi-gigabit analog information signal for a signal path, comprising the steps of:

(1) sampling the multi-gigabit analog information signal at a plurality of phases;

(2) measuring an equalization quality of the samples from one of the plurality of phases;

(3) equalizing the samples from each of the phases based on the measured equalization quality of the one phase, wherein the equalizing includes minimizing differences between an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples; and

(4) quantizing the equalized samples.

12. A method for adaptively equalizing time staggered portions of a plurality of multi-gigabit analog information signals for respective signal paths, comprising the steps of:

(1) generating clock signals from the plurality multi-gigabit analog information signals;

(2) sampling each of the multi-gigabit analog information signals at a plurality of phases of the respective clock signals;

(3) measuring an equalization quality of the samples from one of the plurality of phases for each of the multi-gigabit analog information signals;

(4) equalizing the samples from each of the phases of each of the multi-gigabit analog information signals based on the measured equalization quality of the one phase of each of the respective multi-gigabit analog information signals, wherein the equalizing includes minimizing differences between an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples; and

(5) quantizing the equalized samples.

13. A method for adaptively equalizing a plurality of multi-gigabit analog information signals for respective signal paths, comprising the steps of:

(1) generating a clock signal for each of the multi-gigabit analog information signals from each of the respective multi-gigabit analog information signals;

(2) sampling each of the multi-gigabit analog information signals according to the respective clock signals;

(3) performing an equalizing process on the samples, wherein the equalizing includes minimizing differences between an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples; and

(4) quantizing the equalized samples.

14. A system for quantizing a multi-gigabit serial analog information signal, comprising:

a sampler configured to sample a multi-gigabit analog signal to generate analog samples;

an equalizer coupled to said sampler and configured to minimize inter-symbol interferences in samples output from said sampler, said equalizer including a finite impulse response (“

FIR”

) having at least one adjustable tap;

a quantizer coupled to said equalizer and configured to quantize equalized samples output from said equalizer; and

control logic coupled to said FIR , said control logic including;

a difference detector including a steady-state path, a post-transition path, and a combiner, wherein said combiner is configured to output an average difference between post-transition amplitudes of the equalized samples and steady-state amplitudes of the equalized samples; and

a state machine coupled to one or more outputs of said difference detector and configured to generate said tap updates for said FIR according to said average difference.

15. The system according to claim 14, wherein said control logic further comprises:

a first input coupled to an output of said equalizer;

an analog-to-digital converter (“

ADC”

) coupled to said first input; and

a control module coupled to an output of said ADC;

wherein said ADC is configured to generate multi-level representations of equalized samples, and wherein said control module is configured to generate tap updates from at least said multi-level representations of the equalized samples.

16. The system according to claim 14, wherein said control logic further comprises:

a second input coupled to an output of said quantizer; and

a least-means-squared (“

LMS”

) module coupled to said first and second control logic inputs;

wherein said LMS module is configured to compare the multi-level representations of equalized samples with the quantized samples from said quantizer, and to generate said tap updates according to the comparison.

17. A system for routing and adaptively equalizing high data rate analog data signals, comprising:

a backplane having a plurality of signal paths; and

at least one interface board coupled to said backplane, said interface board including a plurality of receivers coupled to said backplane signal paths, each said receiver including an adaptive equalizer;

wherein each said adaptive equalizer is configured to adapt to an associated backplane signal path to equalize an analog data signal received from said associated backplane signal path; and

wherein each said adaptive equalizer is configured to minimize differences between an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples.