Method and apparatus for reducing a crest factor of a multi-tone data signal

• US 7,286,605 B2
• Filed: 09/30/2003
• Issued: 10/23/2007
• Est. Priority Date: 09/30/2003
• Status: Expired due to Fees

• Current Assignee: Lantiq Beteiligungs-GmbH & Company KG (Intel Corporation)
• Original Assignee: Infineon Technologies AG
• Inventors: Laaser, Peter
• Primary Examiner(s): Tran; Khai
• Application Number:
  US10/674,748
• Publication Number:
  US 20050069045A1
• Time in Patent Office: 1,484 Days
• Field of Search: 375/260, 375/295, 375/296, 375/254, 375/346, 375/285, 375/222
• US Class Current: 375/260
• CPC Class Codes: H04L 27/2618 Reduction thereof using auxiliary subcarriers

Abstract

A crest factor reduction circuit for reducing a crest factor (CF) of a multi-tone-data signal which is transmitted in a predetermined transmission frequency band,

wherein the crest factor reduction circuit (8) comprises means (34) for subtracting a multi-tone-correction signal from said multi-tone-data signal,

wherein the multi-tone-correction signal comprises a plurality of tone signals having frequencies outside said transmission frequency band.

Claims

1. Method for reducing a crest factor of a multi-tone-data signal which is transmitted in a predetermined transmission frequency band Δ

F, wherein a multi-tone-correction signal is subtracted from said multi-tone-data signal, said multi-tone correction signal comprising a plurality of tone signals having frequencies outside said transmission frequency band Δ

F, and the method comprising the following steps;

(a) storing in a first memory at least one data symbol of a data symbol sequence, each data symbol comprising a predetermined number of data samples s(i) with index i, 0>

=i>

=(N−

1),

(b) comparing the amplitude of each data sample of said data symbol with a first threshold value to detect a data sample peak;

(c) performing the following steps when a data sample peak is detected;

(i) reading a multi-tone-correction signal comprising a corresponding number of correction data samples from a second memory;

(ii) shifting cyclically the read correction data samples of the multi-tone correction signal so that the maximum of said correction data samples coincides with the detected data sample peak;

(iii) scaling of the shifted correction data samples of the multi-tone-correction signal according to a predetermined spectrum mask;

(iv) accumulating the scaled correction data samples of the multi-tone-correction signal in a third memory;

(d) subtracting the accumulated correction data samples of the multi-tone-correction signal from the data samples of said data symbol.

2. Method according to claim 1, wherein the amplitude of each data sample s(i) of said data symbol is compared with the first threshold value and the corresponding neighboured data samples s(i−

m) and s(i+m) are compared with a second threshold value to detect a data sample peak with a high main and a high side amplitude.

3. Method according to claim 2, wherein when a data sample peak with a high main and a high side amplitude is detected at least one single tone-correction signal comprising a tone signal having a frequency within said transmission frequency band Δ

F is subtracted from said multi-tone-data signal.

4. Method according to claim 1, wherein the amplitude of each data sample s(i) of said data symbol is compared with a thired threshold value and the corresponding neighboured data samples s(i−

m) and s(i+m) are compared with the second threshold value to detect a data sample peak with a very high main and a high side amplitude.

5. Method according to claim 4, wherein when a data sample peak with a very high and a high side amplitude is detected, the multi-tone-correction signal comprising a plurality of tone signals having frequencies outside said transmission frequency band, and at least one signal tone-correction signal comprising a tone signal having a frequency within said transmission frequency band Δ

F are subtracted from said multi-tone-data signal.

6. Method according to claim 1, wherein said first threshold value, said second threshold value and said third threshold value are adjusted.

7. Method according to claim 1, wherein that third threshold value is higher than said first threshold value.

8. Method according to claim 1, wherein said second threshold value is lower than said first threshold value.

9. Method according to claim 1, wherein said multi-tone-data signal comprises a plurality of tone-signals having frequencies which are equidistant.

10. Method according to claim 1, wherein said multi-tone-data signal is a DMT (Discrete-Multi-tone Transmission) signal.

11. Method according to claim 1, wherein the multi-tone-data signal is an ADSL-signal.

12. A crest factor reduction circuit for reducing a crest factor of a multi-tone-data signal which is transmitted in a predetermined transmission frequency band Δ

F, wherein the crest factor reduction circuit comprises means for subtracting a multi-tone-correction signal from said multi-tone-data signal, wherein the multi-tone-correction signal comprises a plurality of tone signals having frequencies outside said transmission frequency band Δ

F, wherein the crest factor reduction circuit has a data input for receiving a data symbol sequence of a data transmission signal, and wherein a first memory is provided for storing at least one data symbol of the received data symbol sequence, each data symbol comprising a predetermined number of data samples.

13. Crest factor reduction circuit according to claim 12, wherein the crest factor reduction circuit comprises a first comparator for comparing the amplitudes of each data sample s(i) of the stored data symbol with a first threshold value to detect a data sample peak.

14. Crest factor reduction circuit according to claim 13, wherein the crest factor reduction circuit comprises a Counter-Modulo-N which controls a multiplexer for switching sequentially the data samples to the first comparator.

15. Crest factor reduction circuit according to claim 12, wherein a delay unit is provided for delaying the received data samples with a predetermined delay time.

16. Crest factor reduction circuit according to claim 12, wherein the crest factor reduction circuit comprises a data output for outputting the corrected data samples as a sequence of corrected data symbols each comprising a predetermined number of corrected data samples.

17. Crest factor reduction circuit according to claim 16, wherein the data output of the crest factor reduction circuit is connected to a transmission signal path comprising:

(a) a digital filter for forming a digital transmission signal,

(b) a digital analog converter for converting the digital transmission signal into an analog transmission signal, and

(c) an analog filter for forming the analog transmission signal and a line driver for amplifying the analog transmission signal.

18. Crest factor reduction circuit according to claim 17, wherein the crest factor reduction circuit further comprises a convoluting unit for convoluting the received data samples with the impulse response of the transmission signal path.

19. Crest factor reduction circuit according to claim 12, wherein the crest factor reduction circuit comprises the first comparator for comparing the amplitudes of each data sample s(i) of the stored data symbol with the first threshold value and further comprises a second comparator for comparing the amplitudes of the corresponding neighboured data samples s(i−

m) and s(i+m) with a second threshold value to detect a data sample peak with a high main and a high side amplitude.

20. Crest factor reduction circuit according to claim 12, wherein the crest factor reduction circuit comprises a third comparator for comparing the amplitudes of each data sample s(i) of the stored data symbol with the third threshold value and further comprises the second comparator for comparing the amplitudes of the corresponding neighboured data samples s(i−

m) and s(i+m) with the second threshold value to detect a data sample peak with a very high main and a high side amplitude.

21. Crest factor reduction circuit according to claim 19, wherein the single tone-correction signal is read from said second memory and supplied to the shifting unit when the first comparator and the second comparator detect a data sample peak with a high main and a high side amplitude.

22. Crest factor reduction circuit according to claim 19, wherein the multi-tone-correction signal and the single tone-correction signal are read from said second memory and supplied to the shifting unit when the third comparator and the second comparator detect a data sample peak with a very high main and a high side amplitude.

23. Crest factor reduction circuit according to claim 12, wherein the first memory is a RAM (Random Access Memory).

24. A crest factor reduction circuit for reducing a crest factor of a multi-tone-data signal which is transmitted in a predetermined transmission frequency band Δ

F, wherein the crest factor reduction circuit comprises means for subtracting a multi-tone-correction signal from said multi-tone-data signal, wherein the multi-tone-correction signal comprises a plurality of tone signals having frequencies outside said transmission frequency band Δ

F, and wherein a second memory is provided for storing at least one multi-tone-correction signal comprising correction data samples, wherein the number of correction data samples corresponds to a number of data samples of a data symbol.

25. Crest factor reduction circuit according to claim 24, wherein a shifting unit is provided for shifting the correction data samples read from said second memory so that the maximum of the correction data samples coincides with a detected data sample peak.

26. Crest factor reduction circuit according to claim 25, wherein a scaling unit is provided for scaling the shifted correction data samples according to a predetermined spectrum mask.

27. Crest factor reduction circuit according to claim 26, wherein an accumulating unit is provided for accumulating the scaled correction data samples in a third memory.

28. Crest factor reduction circuit according to claim 27, wherein a subtractor is provided for subtracting the accumulated correction data samples from said data samples of the said received data symbol.

29. Crest factor reduction circuit according to claim 27, wherein the third memory is reset by an overflow signal of said modulo-N-counter.

30. Crest factor reduction circuit according to claim 27, wherein the third memory is a RAM (Random Access Memory).

31. Crest factor reduction circuit according to claim 24, wherein the second memory further stores at least one single tone correction signal, wherein the single tone-correction signal comprises a tone-signal having a frequency within the transmission frequency band.

32. Crest factor reduction circuit according to claim 24, wherein the second memory is a RAM (Random Access Memory).

33. A transceiver for transceiving a data signal comprising:

(a) a coding unit for generating a multi-tone-signal from a received data bit stream;

(b) a IFFT unit for performing an inverse fast fourier transformation to generate a multi-tone-data signal comprising a sequence of data symbols, each having a predetermined number (N) of data samples s(i) with index i, 0<

=i<

=(N−

1);

(c) a crest factor reduction circuit for reducing a crest factor of the multi-tone-data signal which is transmitted in a predetermined transmission frequency band, wherein the crest factor reduction circuit comprises means for subtracting a multi-tone-correction signal from said multi-tone-data signal, wherein the multi-tone-correction signal comprises a plurality of tone signals having frequencies outside said transmission frequency band; and

(d) a transmission signal path for forming an analog transmission signal from the corrected multi-tone-data signal.

34. Transceiver according to claim 33, wherein the transmission signal path comprises a digital filter for forming a digital data transmission signal, a digital analog converter for converting the output signal of the digital filter into an analog signal, a analog filter for forming a analog transmission signal and a driving circuit for amplifying the analog transmission signal.

35. Transceiver according to claim 33, wherein the transceiver comprises a reception signal path.

36. Transceiver according to claim 35, wherein the reception signal path comprises an analog filter for limiting the frequency band of a received analog signal, an analog digital converter for converting the received analog signal into a digital signal and a digital filter for forming the received converted digital signal.

37. Transceiver according to claim 33, wherein an echo cancellation unit is provided for compensating echo signals.

38. Transceiver according to claim 37, wherein a subtractor is provided for subtracting the output signal of the echo compensating unit from the output signal of the reception signal path.

39. Transceiver according to claim 38, wherein a FFT-unit is provided for performing a fast fourier transformation of the output signal of the subtractor.

40. Transceiver according to claim 39, wherein a decoding unit is connected to the FFT-unit for performing a multi-tone demodulation.

41. Transceiver according to 33, wherein a hybrid circuit is provided which is connected to the output of the transmission signal path and to the input of the reception signal path.

42. Transceiver according to claim 33, wherein the transceiver is an ADSL-transceiver.