Integrated circuit memory device with delayed write command processing

• US 7,287,119 B2
• Filed: 03/02/2007
• Issued: 10/23/2007
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Nguyen, David, Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Davis, Paul G., Abhyankar, Abhijit M., Gasbarro, James A.
• Primary Examiner(s): Bataille; Pierre-Michel
• Application Number:
  US11/681,384
• Publication Number:
  US 20070159912A1
• Time in Patent Office: 235 Days
• Field of Search: 711/167, 711/154, 711/5, 711/104, 365/189.04, 365/189.01, 365/189, 365/189.03, 365/230.05, 365/233, 365/233.5
• US Class Current: 711/105
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.

Claims

1. An integrated circuit memory device comprising:

a memory core including a plurality of memory cells;

a first set of pins coupled to the memory core, the first set of pins to receive a row address that identifies a row of the memory core, followed by a column address that identifies a column location of the row;

a second set of pins coupled to the memory core, the second set of pins to receive a sense command followed by a write command, wherein the sense command specifies sensing of the row, wherein the write command specifies that the memory device receive write data to be stored at the column location, wherein the write command is presented internally to the memory device after a first delay time has transpired from when the write command is received at the second set of pins;

a third set of pins to receive the write data after a second delay time has transpired from when the write command is received at the second set of pins; and

a column access path coupled to the third set of pins and the memory core, the column access path to convey the write data to the column location.

2. The integrated circuit memory device of claim 1, wherein:

the second set of pins receive a read command; and

the third set of pins are used to output read data in response to the read command, wherein the read data is output after a third delay time has transpired from when the read command is received, wherein the second delay time is based on the third delay time.

3. The integrated circuit memory device of claim 2, wherein the second delay time is based on the third delay time such that the second delay time matches the third delay time minus a channel turnaround time.

4. The integrated circuit memory device of claim 2, further comprising a pin to receive a clock signal, wherein, for every pin of the third set of pins, at least two bits of the read data are output during a clock cycle of the clock signal.

5. The integrated circuit memory device of claim 1, further comprising a pin to receive a clock signal, wherein the third set of pins receive two consecutive bits of the write data, for every pin of the third set of pins, during a clock cycle of the clock signal.

6. The integrated circuit memory device of claim 1, further comprising a plurality of sense amplifiers to store the write data to the memory core, and wherein the plurality of memory cells are dynamic memory cells.

7. An integrated circuit memory device comprising:

a memory core including a plurality of memory banks;

a first interface coupled to the memory core, wherein the first interface is configured to receive an activate command, a row address, a bank address that is associated with the activate command, a write command, a column address, and a bank address that is associated with the write command, wherein;

the activate command specifies that the memory device sense a row of the memory core, wherein the row is identified by the row address and is located in a bank of the memory core identified by the bank address that is associated with the activate command; and

the write command specifies that the memory device receive write data and store the write data to a storage location identified by the column address, wherein the storage location is located in the bank identified by the bank address that is associated with the write command; and

a second interface including a plurality of pins, to receive, after a delay time has transpired from when the write command is received at the first interface, two consecutive bits of the write data for every pin of the plurality of pins during a clock cycle of a clock signal.

8. The integrated circuit memory device of claim 7, wherein the activate command, the row address and the bank address that is associated with the activate command are included in a first packet and the write command, the column address, and the bank address that is associated with the write command are included in a second packet.

9. The integrated circuit memory device of claim 8, wherein the first interface further comprises:

a first set of pins to receive the first packet; and

a second set of pins to receive the second packet.

10. The integrated circuit memory device of claim 7, wherein the first interface further comprises:

a first set of pins to receive the activate command and the write command; and

a second set of pins to receive the row address and the column address.

11. The integrated circuit memory device of claim 10, wherein

the first set of pins receives the activate command during a first command cycle and the write command during a second command cycle;

and

the second set of pins receives the row command during the first command cycle and the column address during the second command cycle.

12. An integrated circuit memory device comprising:

a memory core including a plurality of memory banks;

means for receiving a sense command, a row address, a bank address that is associated with the sense command, a write command, a column address, and a bank address that is associated with the write command, wherein;

the sense command specifies that the memory device sense a row of the memory core, wherein the row is identified by the row address and is located in a bank of the memory core identified by the bank address that is associated with the sense command; and

the write command specifies that the memory device receive write data and store the write data to a storage location identified by the column address, wherein the storage location is located in the bank identified by the bank address that is associated with the write command; and

means for receiving, after a delay time has transpired from when the write command is received, two consecutive bits of the write data, in sequence, during a clock cycle of a clock signal.

13. A method of operation of an integrated circuit memory device having a memory core including a plurality of memory cells, the method comprising:

receiving a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells included in the memory core;

receiving a bank address that identifies a bank of the memory core that contains the row;

while receiving the sense command, receiving a row address that identifies the row;

receiving a write command that specifies that the memory device receive write data;

while receiving the write command, receiving a column address that identifies a column location of an activated row in which to store the write data;

receiving a bank address that identifies a bank of the memory core that contains the column location;

applying the write command internally within the memory device after a first delay time transpires from receiving the write command; and

receiving the write data after a second delay time has transpired from receiving the write command.

14. The method of claim 13, wherein the sense command is included in a first control packet and the write command is included in a second control packet.

15. The method of claim 14, wherein the row address and the bank address that identifies the bank of the memory core that contains the row are included in the first packet, and wherein the column address and the bank address that identifies the bank of the memory core that contains the column location are included in the second packet.

16. The method of claim 13, further comprising;

receiving a clock signal; and

wherein receiving the write data further includes receiving two consecutive bits of the write data at a pin of the integrated circuit memory device during a clock cycle of the clock signal.

17. The method of claim 13, further comprising:

receiving a read command that specifies that the memory device output data; and

,

outputting data from the memory device after a third delay time transpires from receiving the read command, wherein the second delay time is based on the third delay.

18. The method of claim 17, wherein the second delay time corresponds to the third delay time minus a channel turnaround time.

19. A method of operation of an integrated circuit memory device having a memory core including a plurality of memory cells, the method comprising:

receiving a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells included in the memory core;

while receiving the sense command, receiving a row address that identifies the row;

receiving a write command that specifies that the memory device receive write data;

after a first delay time transpires from when the write command is received, applying a control signal to store the write data in the row, in response to the write command; and

receiving the write data after a second delay time has transpired from receiving the write command.

20. The method of claim 19, further comprising;

receiving a clock signal; and

while receiving the write command, receiving a column address that identifies a column location in the row to store the write data; and

wherein receiving the write data includes receiving two consecutive bits of the write data at a pin of the integrated circuit memory device during a clock cycle of the clock signal.

21. A method of operating an integrated circuit memory device that receives clock signals and includes a memory core having a plurality of banks, the method comprising:

providing a sense command to the memory device, wherein the sense command specifies that the memory device activate a row of memory cells in a bank identified by a first bank address;

providing a row address to the memory device, wherein the row address identifies the row of memory cells in the bank identified by the first bank address;

providing a write command to the memory device after providing the sense command, wherein the write command specifies that the memory device receive write data to be stored in the row of memory cells in a bank identified by a second bank address, wherein the write command is presented internally to the memory device after a first delay time has transpired from when the write command is received;

providing a column address to the memory device, wherein the column address identifies a location within the row of memory cells in the bank identified by the second bank address; and

providing the write data to the memory device after a second delay time has transpired from providing the write command.

22. The method of claim 21, wherein the first bank address is set to be the same as the second bank address.

23. The method of claim 21, wherein the sense command is included in a first control packet and the write command is included in a second control packet.