Integrated circuit memory device with delayed write command processing
DC CAFCFirst Claim
1. An integrated circuit memory device comprising:
- a memory core including a plurality of memory cells;
a first set of pins coupled to the memory core, the first set of pins to receive a row address that identifies a row of the memory core, followed by a column address that identifies a column location of the row;
a second set of pins coupled to the memory core, the second set of pins to receive a sense command followed by a write command, wherein the sense command specifies sensing of the row, wherein the write command specifies that the memory device receive write data to be stored at the column location, wherein the write command is presented internally to the memory device after a first delay time has transpired from when the write command is received at the second set of pins;
a third set of pins to receive the write data after a second delay time has transpired from when the write command is received at the second set of pins; and
a column access path coupled to the third set of pins and the memory core, the column access path to convey the write data to the column location.
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Abstract
An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.
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Citations
23 Claims
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1. An integrated circuit memory device comprising:
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a memory core including a plurality of memory cells; a first set of pins coupled to the memory core, the first set of pins to receive a row address that identifies a row of the memory core, followed by a column address that identifies a column location of the row; a second set of pins coupled to the memory core, the second set of pins to receive a sense command followed by a write command, wherein the sense command specifies sensing of the row, wherein the write command specifies that the memory device receive write data to be stored at the column location, wherein the write command is presented internally to the memory device after a first delay time has transpired from when the write command is received at the second set of pins; a third set of pins to receive the write data after a second delay time has transpired from when the write command is received at the second set of pins; and a column access path coupled to the third set of pins and the memory core, the column access path to convey the write data to the column location. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit memory device comprising:
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a memory core including a plurality of memory banks; a first interface coupled to the memory core, wherein the first interface is configured to receive an activate command, a row address, a bank address that is associated with the activate command, a write command, a column address, and a bank address that is associated with the write command, wherein; the activate command specifies that the memory device sense a row of the memory core, wherein the row is identified by the row address and is located in a bank of the memory core identified by the bank address that is associated with the activate command; and the write command specifies that the memory device receive write data and store the write data to a storage location identified by the column address, wherein the storage location is located in the bank identified by the bank address that is associated with the write command; and a second interface including a plurality of pins, to receive, after a delay time has transpired from when the write command is received at the first interface, two consecutive bits of the write data for every pin of the plurality of pins during a clock cycle of a clock signal. - View Dependent Claims (8, 9, 10, 11)
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12. An integrated circuit memory device comprising:
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a memory core including a plurality of memory banks; means for receiving a sense command, a row address, a bank address that is associated with the sense command, a write command, a column address, and a bank address that is associated with the write command, wherein; the sense command specifies that the memory device sense a row of the memory core, wherein the row is identified by the row address and is located in a bank of the memory core identified by the bank address that is associated with the sense command; and the write command specifies that the memory device receive write data and store the write data to a storage location identified by the column address, wherein the storage location is located in the bank identified by the bank address that is associated with the write command; and means for receiving, after a delay time has transpired from when the write command is received, two consecutive bits of the write data, in sequence, during a clock cycle of a clock signal.
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13. A method of operation of an integrated circuit memory device having a memory core including a plurality of memory cells, the method comprising:
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receiving a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells included in the memory core; receiving a bank address that identifies a bank of the memory core that contains the row; while receiving the sense command, receiving a row address that identifies the row; receiving a write command that specifies that the memory device receive write data; while receiving the write command, receiving a column address that identifies a column location of an activated row in which to store the write data; receiving a bank address that identifies a bank of the memory core that contains the column location; applying the write command internally within the memory device after a first delay time transpires from receiving the write command; and receiving the write data after a second delay time has transpired from receiving the write command. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method of operation of an integrated circuit memory device having a memory core including a plurality of memory cells, the method comprising:
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receiving a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells included in the memory core; while receiving the sense command, receiving a row address that identifies the row; receiving a write command that specifies that the memory device receive write data; after a first delay time transpires from when the write command is received, applying a control signal to store the write data in the row, in response to the write command; and receiving the write data after a second delay time has transpired from receiving the write command. - View Dependent Claims (20)
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21. A method of operating an integrated circuit memory device that receives clock signals and includes a memory core having a plurality of banks, the method comprising:
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providing a sense command to the memory device, wherein the sense command specifies that the memory device activate a row of memory cells in a bank identified by a first bank address; providing a row address to the memory device, wherein the row address identifies the row of memory cells in the bank identified by the first bank address; providing a write command to the memory device after providing the sense command, wherein the write command specifies that the memory device receive write data to be stored in the row of memory cells in a bank identified by a second bank address, wherein the write command is presented internally to the memory device after a first delay time has transpired from when the write command is received; providing a column address to the memory device, wherein the column address identifies a location within the row of memory cells in the bank identified by the second bank address; and providing the write data to the memory device after a second delay time has transpired from providing the write command. - View Dependent Claims (22, 23)
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Specification