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High speed synchronization in dual-processor safety controller

  • US 7,287,184 B2
  • Filed: 09/16/2003
  • Issued: 10/23/2007
  • Est. Priority Date: 09/16/2003
  • Status: Active Grant
First Claim
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1. A safety controller comprising:

  • a first and second processing unit communicating on a communication bus, each including a processor and memory, the memory of each of the first and second processing units loadable with a common safety program and input/output variables, wherein the safety program is repeatably executable to read input variables representing inputs from external controlled devices and write output variables representing outputs to external controlled devices at least one processor including a buffer receiving a plurality of input variables asynchronously from I/O circuits connected to sensors;

    a coordinator program providing each of the first and second processing units with identical copies of the input variables from the buffer at a predetermined point in the repeated execution of the common safety programs;

    a synchronization program executable by the first and second processing units to execute the common safety programs based on the identical copies and to compare execution of the common safety programs and to enter a safety state when this execution differs.

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