Method for monitoring a microprocessor and circuit arrangement having a microprocessor
First Claim
1. A method for monitoring a microprocessor using an assigned watchdog, comprising:
- causing the watchdog to monitor a reception of a reset pulse within a time interval of a predetermined duration;
causing the watchdog to initiate a reset of the microprocessor if the reset pulse is not received; and
executing at least one check function of the watchdog in an operating phase of the microprocessor, each one of the at least one check function including a reset of the watchdog and an execution of a sequence of waiting loops, wherein a duration of the execution of the sequence of waiting loops of at least one of the at least one check function is greater than the predetermined duration of the time interval;
incrementing a counter with the execution of the at least one check function, the execution of the at least one check function being a function of a content of the counter;
wherein;
the counter has four counter contents,an analysis is performed at one of the four counter contents, andthe least one check function is executed each time at the other counter contents.
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Abstract
A method for monitoring a microprocessor and a circuit arrangement having a microprocessor are described. A microprocessor is monitored using an assigned watchdog. The watchdog monitors whether reset pulses are received within a time interval of predetermined duration. If the reset pulse is received, the time interval is reset and restarted. If reset pulses are not received, a reset of the microprocessor is initiated. In suitable operating phases of the microprocessor, a check function of the watchdog is activated. During the execution of the check function, first a reset of the watchdog is executed and then a sequence of waiting loops, whose duration is greater than the duration of the time interval of the watchdog, is executed.
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Citations
12 Claims
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1. A method for monitoring a microprocessor using an assigned watchdog, comprising:
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causing the watchdog to monitor a reception of a reset pulse within a time interval of a predetermined duration; causing the watchdog to initiate a reset of the microprocessor if the reset pulse is not received; and executing at least one check function of the watchdog in an operating phase of the microprocessor, each one of the at least one check function including a reset of the watchdog and an execution of a sequence of waiting loops, wherein a duration of the execution of the sequence of waiting loops of at least one of the at least one check function is greater than the predetermined duration of the time interval; incrementing a counter with the execution of the at least one check function, the execution of the at least one check function being a function of a content of the counter; wherein; the counter has four counter contents, an analysis is performed at one of the four counter contents, and the least one check function is executed each time at the other counter contents. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit arrangement, comprising:
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a counter; a microprocessor; a watchdog assigned to the microprocessor and for performing a reset of the microprocessor if a reset pulse is not received within a time interval of predetermined duration, wherein; a different clock signal is supplied to the watchdog than to the microprocessor; a non-volatile memory to which is assigned the microprocessor, at least a counter content of the counter being stored in the non-volatile memory; and an at least one check function of the watchdog, wherein the check function is executed in an operating phase of the microprocessor, each one of the at least one check function including a reset of the watchdog and an execution of a sequence of waiting loops, wherein the duration of the execution of the sequence of waiting loops of at least one of the at least one check function is greater than the predetermined duration of the time interval; wherein the counter is incremented with the execution of the at least one check function, the execution of the at least one check function being a function of a content of the counter, and wherein; the counter has a plurality of counter contents, an analysis is performed at one of the plurality of counter contents, and the least one check function is executed each time at the other counter contents. - View Dependent Claims (10, 11)
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12. A memory component storing a computer program that when executed on a microprocessor results in a performance of the following:
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causing a watchdog to monitor a reception of a reset pulse within a time interval of a predetermined duration; causing the watchdog to initiate a reset of the microprocessor if the reset pulse is not received; and executing at least one check function of the watchdog in an operating phase of the microprocessor, each one of the at least one check function including a reset of the watchdog and an execution of a sequence of waiting loops, wherein a duration of the execution of the sequence of waiting loops of at least one of the at least one check function is greater than the predetermined duration of the time interval; incrementing a counter with the execution of the at least one check function, the execution of the at least one check function being a function of a content of the counter; wherein; the counter has a plurality of counter contents, an analysis is performed at one of the plurality of counter contents, and the least one check function is executed each time at the other counter contents.
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Specification