Convolutional encoder and method of operation

• US 7,287,210 B2
• Filed: 09/26/2002
• Issued: 10/23/2007
• Est. Priority Date: 09/28/2001
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: MacDougall, Scott
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US10/255,278
• Publication Number:
  US 20030074627A1
• Time in Patent Office: 1,853 Days
• Field of Search: 714/786, 714/746, 714/792, 714/795
• US Class Current: 714/786
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes

Abstract

Convolutionally encoding a data stream includes inputting a first block of two or more bits in parallel into a shift register. A number of intermediate calculations are performed in parallel using a number of respective delayed shift register outputs; and said number of intermediate calculations are output to form a convolutionally encoded sequence.

In one example, a register (of individual bits stored in words), is set up. The register is longer than the constraint length means that a relatively large number of input bits can be read from memory only once, thus avoiding many independent moves of operands to and from memory. Since the register is longer than the constraint length, the register need only be shifted once for every ‘a+1’ input bits, rather than once for each bit.

Claims

1. A method of convolutionally encoding a data stream comprising:

inputting a first block of two or more bits in parallel into a first portion of a plurality of data registers arranged to operate as a shift register;

performing a number of first intermediate calculations in parallel using a number of outputs from the plurality of data registers;

storing a number of first intermediate calculations in a second portion of the plurality of data registers; and

using one or more of said stored number of first intermediate calculations with data stored in the first portion of the plurality of data registers to perform second intermediate calculations to be stored in the plurality of data registers; and

calculating a final convolutionally encoded output from the plurality of data registers.

2. The method of convolutionally encoding a data stream according to claim 1, the method further comprising:

inputting a second block of two or more bits in parallel of said data stream into said plurality of data registers arranged to operate as a shift register, when said first or second intermediate calculations have been performed; and

performing further intermediate calculations on a number of respective outputs from the plurality of data registers.

3. The method of convolutionally encoding a data stream according to claim 2, wherein the step of inputting a second block includes the steps of:

shifting register bit values by two or more bits per cycle; and

reading two or more new input bits into the plurality of data registers arranged to operate as a shift register.

4. The method of convolutionally encoding a data stream according to claim 1, the method further comprising:

configuring or selecting a portion of a plurality of data registers arranged to operate as a shift register such that said two or more bits input in parallel is longer than a constraint length of the convolutionally encoded sequence to be output.

5. The method of convolutionally encoding a data stream according to claim 1, the method further comprising:

inputting said two or more bits into said first portion of a plurality of data registers arranged to operate as a shift register as individual words.

6. A convolutional encoder adapted to perform the method steps of claim 1.

7. A communication unit adapted to perform the convolutional encoding method steps of claim 1.

8. A communication system adapted to facilitate the convolutional encoding method steps of claim 1.

9. A convolutional encoder for convolutionally encoding a data stream the convolutional encoder comprising:

one or more input pods;

a plurality of data registers arranged to operate as a shift register operably coupled to said one or more input ports for receiving into a first portion of the plurality of data registers a first block of two or more bits in parallel of said data stream;

calculation means, operably coupled to said plurality of data registers arranged to operate as a shift register to perform logical calculations on outputs from said plurality of data registers; and

one or more output ports, operably coupled to said calculation means, to output a convolutionally encoded data stream;

wherein said

calculation means is arranged to perform a number of first intermediate calculations in parallel using a number of outputs from the plurality of data registers;

a second portion of said plurality of data registers is arranged to store a number of first intermediate calculations; and

said calculation means is arranged to re-use one or more of said stored number of first intermediate calculations with data stored in the first portion of a plurality of data registers to perform second intermediate calculations to be stored in the plurality of data registers and generate a final convolutionally encoded output from the plurality of data registers.

10. The convolutional encoder according to claim 9, comprising said calculation means performing said intermediate calculations in a series of pre-determined stages.

11. The convolutional encoder according to claim 9, further comprising said plurality of data registers receiving a second block of two or more bits of said data stream in parallel when intermediate calculations have been performed and said calculation means is arranged to perform further intermediate calculations using said second block of two or more bits and a number of outputs from the plurality of data registers.

12. The convolutional encoder according to claim 9, further comprising said second block of bits being input to said plurality of data registers by shifting register bit values by said two or more bits per cycle;

followed by inputting two or more new input bits from said data stream into said plurality of data registers.

13. The convolutional encoder according to claim 9, further comprising said two or more bits input in parallel being longer than a constraint length of the convolutionally encoded sequence to be output.

14. The convolutional encoder according to claim 9, further comprising said plurality of data registers receiving said two or more bits in parallel as individual words.

15. A communication unit comprising the convolutional encoder of claim 9.

16. A communication system comprising the communication unit of claim 15.