Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions

• US 7,288,457 B2
• Filed: 09/14/2004
• Issued: 10/30/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Kreps, Scott A.
• Primary Examiner(s): Pham; Long
• Application Number:
  US10/940,594
• Publication Number:
  US 20050118767A1
• Time in Patent Office: 1,141 Days
• Field of Search: 438/197, 438/285
• US Class Current: 438/285
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain regions. The superlattice may include a plurality of stacked groups of layers. The superlattice may have upper portions extending above adjacent upper portions of the source and drain regions, and lower portions contacting the source and drain regions so that a channel is defined in lower portions of the superlattice. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The method may further include forming a gate overlying the superlattice.

Claims

1. A method for making a semiconductor device comprising:

providing a semiconductor substrate; and

forming at least one metal oxide semiconductor field-effect transistor (MOSFET) by

forming spaced apart source and drain regions and a superlattice on the semiconductor substrate so that the superlattice is between the source and drain regions, the superlattice comprising a plurality of stacked groups of layers and having upper portions extending above adjacent upper portions of the source and drain regions and lower portions contacting the source and drain regions so that a channel is defined in lower portions of the superlattice,

each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

forming a gate overlying the superlattice.

2. The method of claim 1 wherein each of the source and drain regions comprises a respective epitaxial silicon layer.

3. The method of claim 2 wherein the superlattice has a greater thickness than the epitaxial silicon layers.

4. The method of claim 1 wherein the source and drain regions each have a respective trench therein adjacent the superlattice;

and wherein the upper portions of the superlattice extend above bottom portions of the trenches.

5. The method of claim 1 wherein forming the gate comprises forming an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.

6. The method of claim 1 further comprising forming a contact layer on at least one of the source and drain regions.

7. The method of claim 1 wherein the superlattice has a common energy band structure therein.

8. The method of claim 1. wherein the superlattice has a higher charge carrier mobility than would otherwise be present without the non-semiconductor layer.

9. The method of claim 1 wherein each base semiconductor portion comprises silicon.

10. The method of claim 1 wherein each base semiconductor portion comprises germanium.

11. The method of claim 1 wherein each energy band-modifying layer comprises oxygen.

12. The method of claim 1 wherein each energy band-modifying layer is a single monolayer thick.

13. The method of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

14. The method of claim 1 wherein the superlattice further has a substantially direct energy bandgap.

15. The method of claim 1 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

16. The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.

17. The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

18. The method of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

19. A method for making a semiconductor device comprising:

providing a semiconductor substrate; and

forming at least one metal oxide semiconductor field-effect transistor (MOSFET) by

forming spaced apart source and drain regions and a superlattice on the semiconductor substrate so that the superlattice is between the source and drain regions, the source and drain regions each having a respective trench therein adjacent the superlattice, and the superlattice having upper portions extending above bottom portions of the trenches and lower portions contacting the source and drain regions so that a channel is defined in lower portions of the superlattice,

each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

forming a gate overlying the superlattice by forming an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.

20. The method of claim 19 further comprising forming a contact layer on at least one of the source and drain regions.

21. The method of claim 19 wherein the superlattice has a common energy band structure therein.

22. The method of claim 19 wherein the superlattice has a higher charge carrier mobility than would otherwise be present without the non-semiconductor layer.

23. The method of claim 19 wherein each base semiconductor portion comprises silicon.

24. The method of claim 19 wherein each base semiconductor portion comprises germanium.

25. The method of claim 19 wherein each energy band-modifying layer comprises oxygen.

26. The method of claim 19 wherein each energy band-modifying layer is a single monolayer thick.

27. The method of claim 19 wherein each base semiconductor portion is less than eight monolayers thick.

28. The method of claim 19 wherein the superlattice further has a substantially direct energy bandgap.

29. The method of claim 19 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

30. The method of claim 19 wherein all of the base semiconductor portions are a same number of monolayers thick.

31. The method of claim 19 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

32. The method of claim 19 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

33. A method for making a semiconductor device comprising:

providing a semiconductor substrate; and

forming at least one metal oxide semiconductor field-effect transistor (MOSFET) by

forming spaced apart source and drain regions and a superlattice on the semiconductor substrate so that the superlattice is between the source and drain regions, the source and drain regions each comprising a respective epitaxial silicon layer, and the superlattice comprising a plurality of stacked groups of layers,

the superlattice having a greater thickness than the epitaxial silicon layers, and lower portions of the superlattice being in contact with the epitaxial silicon layers so that a channel is defined in lower portions of the superlattice,

each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

forming a gate overlying the superlattice by forming an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.

34. The method of claim 33 further comprising forming a contact layer on at least one of the source and drain regions.

35. The method of claim 33 wherein the superlattice has a common energy band structure therein.

36. The method of claim 33 wherein the superlattice has a higher charge carrier mobility than would otherwise be present without the non-semiconductor layer.

37. The method of claim 33 wherein each base semiconductor portion comprises silicon.

38. The method of claim 33 wherein each base semiconductor portion comprises germanium.

39. The method of claim 33 wherein each energy band-modifying layer comprises oxygen.

40. The method of claim 33 wherein each energy band-modifying layer is a single monolayer thick.

41. The method of claim 33 wherein each base semiconductor portion is less than eight monolayers thick.

42. The method of claim 33 wherein the superlattice further has a substantially direct energy bandgap.

43. The method of claim 33 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

44. The method of claim 33 wherein all of the base semiconductor portions are a same number of monolayers thick.

45. The method of claim 33 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

46. The method of claim 33 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.