Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner

• US 7,288,475 B2
• Filed: 11/13/2006
• Issued: 10/30/2007
• Est. Priority Date: 01/14/2004
• Status: Expired due to Fees

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Stamper, Anthony K.
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US11/558,959
• Publication Number:
  US 20070087551A1
• Time in Patent Office: 351 Days
• Field of Search: 438617-618, 438622-625, 438/629, 438637-640, 438/666, 438/668, 438/672, 438/700
• US Class Current: 438/623
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/3121 Layers comprising organo-silicon compounds
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO₂. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO₂, SiCOH, or doped silicate glass.

Claims

1. A method of forming an interconnect structure comprising the steps of:

providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric;

depositing a mechanically rigid dielectric atop said lower metal wiring layer;

forming at least one via through said mechanically rigid dielectric to a portion of said first metal lines; and

forming an upper metal wiring layer having second metal lines positioned within a upper low-k dielectric, said second metal lines being electrically connected to said first metal lines through said via, wherein said via comprises a metal having a coefficient of thermal expansion that substantially matches said mechanically rigid dielectric, wherein said lower low-k dielectric and said upper low-k dielectric comprises the same or different dielectric material comprising a b-staged polymer having about 95% carbon or a SiCOH carbon doped oxide.

2. The method of claim 1 wherein said mechanically rigid dielectric comprises a coefficient of thermal expansion ranging from about 0.1 ppm/°

C. to about 5.0 ppm/°

C.

3. The method of claim 1 wherein said mechanically rigid dielectric comprises SiO₂, SiCOH, or doped silicate glass.

4. The method of claim 1 wherein said mechanically rigid dielectric has a thickness ranging from about 100 nm to about 1000 nm.

5. The method of claim 1 wherein said upper low-k dielectric and said lower low-k dielectric have a dielectric constant of less than about 3.5.

6. The method of claim 1 wherein said second metal lines, said first metal lines or a combination of said second metal lines and said first metal lines comprise copper, aluminum, silver, gold or alloys thereof.