Method of manufacturing semiconductor device, method of manufacturing electronic apparatus, semiconductor device, and electronic apparatus

• US 7,288,792 B2
• Filed: 02/22/2005
• Issued: 10/30/2007
• Est. Priority Date: 02/23/2004
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Yudasaka, Ichio
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Nguyen; Joseph
• Application Number:
  US11/061,442
• Publication Number:
  US 20050184293A1
• Time in Patent Office: 980 Days
• Field of Search: 257/59, 257/72, 257/E29.314, 257/758, 257/774, 257/775
• US Class Current: 257/72
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

Exemplary embodiments of the present invention are intended to provide a semiconductor device that can readily address or achieve high integration. Exemplary embodiments provide a semiconductor device constructed to include a transistor and a multi-layer wiring structure electrically connected to the transistor, the multi-layer wiring structure having a first wiring layer disposed in the same layer as the semiconductor layer of the transistor.

Claims

1. A semiconductor device, comprising:

a substrate;

a first semiconductor film positioned over the substrate;

a first wiring positioned over the substrate;

a first insulating layer positioned over the first semiconductor film and the first wiring;

a gate electrode positioned over the first insulating layer, the gate electrode being overlapped with the first semiconductor film;

a second wiring positioned over the first insulating layer, the first wiring being overlapped with the second wiring, the first and second wirings being electrically connected to each other via a first contact hole that is formed in the first insulating layer;

a second insulating layer positioned over the gate electrode and the second wiring; and

a third wiring positioned over the second insulating layer, the third wiring overlapped with the second wiring, the second and the third wirings being electrically connected to each other via a second contact hole that is formed in the second insulating layer;

a source electrode positioned over the second insulating layer, the source electrode overlapped with the first semiconductor film, the source electrode and the first semiconductor film being electrically connected to each other via a third contact hole that is formed in the first and second insulating layers; and

a drain electrode positioned over the second insulating layer, the drain electrode overlapped with the first semiconductor film, the drain electrode and the first semiconductor film being electrically connected to each other via a fourth contact hole that is formed in the first and the second insulating layers.

2. The semiconductor according to claim 1, the first semiconductor film and the first wiring being positioned on a same layer, the first semiconductor film and the first wiring being separated to each other.

3. The semiconductor according to claim 1, the first wiring being electrically connected to the first semiconductor film.

4. The semiconductor according to claim 1, the first wiring being connected to the first semiconductor film, the first wiring and the first semiconductor film being composed of one semiconductor film.

5. The semiconductor according to claim 1, the first wiring being a second semiconductor film

6. The semiconductor according to claim 1, the first wiring being a second semiconductor film, each of the first and the second semiconductor films being a poly silicon film.

7. The semiconductor according to claim 1, each of the gate electrode and the second wiring being a metal film.

8. The semiconductor according to claim 1, a portion of the first semiconductor film being a channel region of a transistor, the portion being overlapped with the gate electrode.

9. The semiconductor according to claim 1, the first semiconductor film and the gate electrode being a component of a transistor, the first, the second and the third wirings being a component of a multi wiring structure, the multi wiring structure being configured to receive an electrical signal from the transistor.

10. A semiconductor device, comprising:

a substrate;

a first semiconductor film positioned over the substrate;

a first wiring positioned over the substrate, the first wiring being a metal film;

a first insulating layer positioned over the first semiconductor film and the first wiring;

a sate electrode positioned over the first insulating layer, the gate electrode being overlapped with the first semiconductor film;

a second wiring positioned over the first insulating layer, the first wiring being overlapped with the second wiring, the first and second wirings being electrically connected to each other via a first contact hole that is formed in the first insulating layer;

a second insulating layer positioned over the gate electrode and the second wiring; and

a third wiring positioned over the second insulating layer, the third wiring overlapped with the second wiring, the second and third wirings being electrically connected to each other via a second contact hole that is formed in the second insulating layer.

11. A semiconductor device, comprising:

a substrate;

a first semiconductor film positioned over the substrate;

a first wiring positioned over the substrate, the first wiring being a metal film that includes aluminum;

a first insulating layer positioned over the first semiconductor film and the first wiring;

a gate electrode positioned over the first insulating layer, the gate electrode being overlapped with the first semiconductor film;

a second wiring positioned over the first insulating layer, the first wiring being overlapped with the second wiring, the first and second wirings being electrically connected to each other via a first contact hole that is formed in the first insulating layer;

a second insulating layer positioned over the sate electrode and the second wiring; and

a third wiring positioned over the second insulating layer, the third wiring overlapped with the second wiring, the second and third wirings being electrically connected to each other via a second contact hole that is formed in the second insulating layer.

12. A semiconductor device, comprising:

a substrate;

a first semiconductor film positioned over the substrate;

a first wiring positioned over the substrate;

a first insulating layer positioned over the first semiconductor film and the first wiring;

a gate electrode positioned over the first insulating layer, the gate electrode being overlapped with the first semiconductor film;

a second insulating layer positioned over the gate electrode; and

a third wiring positioned over the second insulating layer, the third wiring overlapped with the first wiring, the first and the third wirings being electrically connected to each other via a first and a second contact holes, the first contact hole being formed in the first insulating layer, the second contact hole being formed in the second insulating layer;

a source electrode positioned over the second insulating layer, the source electrode overlapped with the first semiconductor film, the source electrode and the first semiconductor film being electrically connected to each other via a third contact hole that is formed in the first and the second insulating layers; and

a drain electrode positioned over the second insulating layer, the drain electrode overlapped with the first semiconductor film, the drain electrode and the first semiconductor film being electrically connected to each other via a fourth contact hole that is formed in the first and the second insulating layers.