Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits

• US 7,288,845 B2
• Filed: 05/08/2003
• Issued: 10/30/2007
• Est. Priority Date: 10/15/2002
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited), Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation), Marvell Semiconductor, Inc. (Marvell Technology Group Limited)
• Inventors: Wu, Albert, Sutardja, Sehat, Lee, Jin-Yuan, Lin, Mou-Shiung
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US10/434,524
• Publication Number:
  US 20040070086A1
• Time in Patent Office: 1,636 Days
• Field of Search: 257/784, 257/781, 257/786, 257/E23.02
• US Class Current: 257/781
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Claims

1. A structure for enabling wire bond connections over active regions of an integrated circuit (IC) die, comprising:

a substrate, in or on which are formed active devices, the die further comprising at least one interconnect metal layer having at least one top level metal contact, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one opening through which is exposed the at least one top level metal contact point;

an adhesion layer formed on the passivation layer; and

a gold bond pad formed directly on the adhesion layer over the passivation layer, connected to said top level metal contact through said opening, said gold bond pad being formed directly over at least one active device.

2. The structure of claim 1 wherein the gold bond pad is formed over said opening in said passivation layer.

3. The structure of claim 1 wherein a bonding location for the gold bond pad is over said opening in said passivation layer.

4. The structure of claim 1 wherein said opening has a minimum width of about 0.5 μ

m.

5. The structure of claim 1 wherein said passivation layer comprises one or more layers of inorganic material.

6. The structure of claim 1 wherein said adhesion layer is Ti, Cr, TiW or TiN.

7. The structure of claim 1 wherein said gold bond pad comprises soft Au having a hardness range of less than about 150 Hv, an Au purity larger than about 97%, and a thickness larger than about 1 μ

m.

8. The structure of claim 1 wherein the adhesion layer is formed over said passivation layer.

9. The structure of claim 1 wherein said passivation opening has a width between 40 μ

m and 100 μ

m.

10. A wire connection structure for an integrated circuit (IC) die, comprising:

semiconductor means for providing at least one of an active device and a passive device and that includes;

dielectric means that is arranged adjacent to said at least one of said active and passive device for providing insulation,

metal interconnect means that is arranged adjacent to said at least one of said active and passive device for providing interconnections, wherein said metal interconnect means defines a contact pad, and

passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad; and

gold bond pad means arranged directly over said passivation means and said active device for absorbing bond pad fabrication stress and for providing a connection to said contact pad through said passivation opening, the gold bond pad means being formed directly on an adhesion layer that is formed on said passivation means and said exposed contact pad.

11. The wire connection structure of claim 10 further comprising wire means for providing a connection to said gold bond pad means and that is bonded to said gold bond pad means in a wire bonding region.

12. The wire connection structure of claim 10 wherein said wire bonding region is formed over said passivation opening.

13. The wire connection structure of claim 10 wherein said passivation means includes one or more layers of inorganic material.

14. The wire connection structure of claim 10 wherein said gold bond pad means includes:

a first layer formed over said adhesion layer;

a second layer formed over said first layer.

15. The wire connection structure of claim 14 wherein said adhesion layer includes at least one of titanium (Ti), chromium (Cr), titanium tungsten (TiW) and titanium nitride (TiN).

16. The wire connection structure of claim 14 wherein said first layer includes gold that is deposited by sputtering.

17. The wire connection structure of claim 14 wherein said second layer includes gold that is deposited by electroplating.

18. The wire connection structure of claim 14 wherein said second layer has a hardness range of less than about 150 Hv, and wherein said gold of said second layer has a purity that is greater than or equal to about 97% and a thickness that is greater than or equal to 1 μ

m.

19. A wire connection structure for an integrated circuit (IC) die, comprising:

semiconductor means for providing at least one of an active device and a passive device and that includes;

dielectric means that is arranged adjacent to said at least one of said active and passive device for providing insulation,

metal interconnect means that is arranged adjacent to said at least one of said active and passive device for providing interconnections, wherein said metal interconnect means defines a contact pad, and

passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad;

gold bond pad means arranged directly over said passivation means and said at least one of said active and passive devices for absorbing wire bonding stress and for providing a connection to said contact means through said passivation opening; and

an adhesion layer formed on said passivation means that includes at least one of Ti, Cr, TiW and TiN, the gold bond pad means being formed directly on the adhesion layer;

a seed layer formed over said adhesion layer that includes gold; and

a bulk layer formed over said seed layer that includes gold.

20. The wire connection structure of claim 19 further comprising a wire that is bonded to said gold bond pad means in a wire bonding region.

21. The wire connection structure of claim 20 wherein said wire bonding region is over said passivation opening.

22. The wire connection structure of claim 19 wherein said bulk layer has a hardness range that is less than or equal to 150 Hv.

23. The wire connection structure of claim 19 wherein said gold has a purity that is greater than or equal to about 97%.

24. The wire connection structure of claim 19 wherein said bulk layer has a thickness that is greater than or equal to about 1 μ

m.

25. The wire connection structure of claim 19 wherein said seed layer is deposited by sputtering.

26. The wire connection structure of claim 19 wherein said bulk layer is deposited by electroplating.

27. A wire connection structure for an integrated circuit (IC) die, comprising:

semiconductor means for providing an active device and that includes;

dielectric means that is arranged adjacent to said active device for providing insulation,

metal interconnect means that is arranged adjacent to said active device for providing interconnections, wherein said metal interconnect means defines a contact pad, and

passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad;

an adhesion layer formed on said passivation means and said exposed contact pad; and

gold bond pad means arranged directly over said passivation means and said active device for absorbing bond pad fabrication stress and for providing a connection to said contact pad through said passivation opening, the gold bond pad means being formed directly on the adhesion layer.

28. A wire connection structure for an integrated circuit (IC) die, comprising:

semiconductor means for providing an active device and that includes;

dielectric means that is arranged adjacent to said active device for providing insulation,

metal interconnect means that is arranged adjacent to said active device for providing interconnections, wherein said metal interconnect means defines a contact pad,

passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad;

gold bond pad means arranged directly over said passivation means and said active device for absorbing bond pad fabrication stress and for providing a connection to said contact means through said passivation opening; and

an adhesion layer formed on said passivation means that includes at least one of Ti, Cr, TiW and TiN, the gold bond pad being formed directly on the adhesion layer, wherein the gold bond pad means includes;

a seed layer formed over said adhesion layer that includes gold; and

a bulk layer formed over said seed layer that includes gold.