Method and apparatus for fail-safe resynchronization with minimum latency

• US 7,288,973 B2
• Filed: 09/27/2005
• Issued: 10/30/2007
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Davis, Paul G., Abhyankar, Abhijit M., Stonecypher, William F., Chan, Andy Peng-Pui, Zerbe, Jared LeVan, Ching, Michael Tak-kei
• Primary Examiner(s): Wells; Kenneth B.
• Assistant Examiner(s): Nguyen; Hai L.
• Application Number:
  US11/237,276
• Publication Number:
  US 20060022724A1
• Time in Patent Office: 763 Days
• Field of Search: 327/141, 327/144, 327/154, 327/162, 327/163, 370/503
• US Class Current: 327/144
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Claims

1. A synchronizer circuit for passing data from circuitry in a first clock domain clocked by a first clock signal to circuitry in a second clock domain clocked by a second clock signal, the first and second clock signals being mesochronous, comprising:

a domain-crossing circuit including at least two parallel data paths and configured to receive an input data signal from the circuitry in the first clock domain and to output at least two data signals in the second clock domain from respective ones of the at least two parallel data paths;

a phase comparator circuit configured to generate an output based on a phase difference between the first and the second clock signals; and

a selecting circuit coupled to receive the at least two data signals and configured to select one of the at least two data signals to pass to the circuitry in the second clock domain based on the output of the phase comparator circuit.

2. The synchronizer circuit of claim 1, wherein the phase comparator circuit includes:

a phase comparator configured to receive the first and second clock signals and a third clock signal in a fixed phase relationship with the second clock signal and to produce an output dependent on the phase difference between the first and second clock signals; and

an integrator coupled to the phase comparator and configured to respond to a control signal such that an integration function in the integrator is turned off when the control signal is in a first state and is turned on when the control signal is in a second state.

3. The synchronizer circuit of claim 1, wherein the phase comparator circuit is further configured to store a plurality of skip values each corresponding to a respective one of a plurality of operating frequencies and to select one of the plurality of skip values corresponding to a current operating frequency of the synchronizer circuit as the output to the selecting circuit.

4. The synchronizer circuit of claim 1, wherein the domain-crossing circuit includes:

a sampling circuit configured to sample the input data signal according to the first clock signal;

a first latch circuit in a first one of the at least two parallel data paths and configured to latch an output from the sampling circuit on a first edge of a third clock signal that is in a fixed phase relationship with the second clock signal; and

a second latch circuit in a second one of the at least two parallel data paths and configured to latch the output from the sampling circuit on a second edge of the third clock signal, the second edge having an opposite direction of transition relative to the first edge.

5. The synchronizer circuit of claim 4, wherein the output from the sampling circuit is differential.

6. The synchronizer circuit of claim 4, wherein each of the first latch circuit and the second latch circuit includes a precharged sense amp.

7. The synchronizer circuit of claim 4, wherein the third clock signal is in quadrature with the second clock signal and is duty-cycle corrected.

8. The synchronizer circuit of claim 4, wherein the domain-crossing circuit further includes a third latch circuit in one of the at least two parallel data paths and configured to retime an output of the first latch circuit.

9. The synchronizer circuit of claim 1, wherein the domain-crossing circuit includes:

a first sampling circuit and a first latch circuit in a first one of the at least two parallel data paths, the first sampling circuit configured to sample the input data signal on rising edges of the first clock signal, the first latch circuit configured to latch an output from the first sampling circuit on an edge of a third clock signal that is in a fixed phase relationship with the second clock signal; and

a second sampling circuit and a second latch circuit in a second one of the at least two parallel data paths, the second sampling circuit configured to sample data in the input data signal on falling edges of the first clock signal, the second latch circuit configured to latch an output from the second sampling circuit on the edge of the third clock signal.

10. The synchronizer circuit of claim 9, wherein the third clock signal is in quadrature with the second clock signal and is duty-cycle corrected.

11. The synchronizer circuit of claim 9, wherein the domain-crossing circuit further includes:

a third sampling circuit and a third latch circuit in a third one of the at least two parallel data paths, the third sampling circuit configured to sample data in the input data signal on rising edges of a fourth clock signal in a fixed phase relationship with the first clock signal, the third latch circuit configured to latch an output from the third sampling circuit on the edge of the third clock signal; and

a fourth sampling circuit and a fourth latch circuit in a fourth one of the at least two parallel data paths, the fourth sampling circuit configured to sample data in the input data signal on falling edges of the fourth clock signal, the fourth latch circuit configured to latch an output from the fourth sampling circuit on the edge of the third clock signal.

12. The synchronizer circuit of claim 1, wherein the at least two data signals include data signals in different latency domains when the phase difference between the first and the second clock signals are in certain ranges, and wherein the phase comparator circuit is further configured to freeze its output to avoid changes in latency in an output of the synchronizer circuit.

13. The synchronizer circuit of claim 12, wherein the phase comparator circuit is further configured to receive a control signal, to freeze its output when the control signal is in a first state, and to allow its output to change when the control signal is in a second state.

14. A method of passing data from circuitry in a first clock domain clocked by a first clock signal to circuitry in a second clock domain clocked by a second clock signal, the first and second clock signals being mesochronous, comprising:

sampling an input data signal from the circuitry in the first clock domain according to the first clock to produce at least one sampled output;

outputting at least two data signals in the second clock domain from at least two parallel data paths; and

selecting one of the at least two data signals to be passed to the circuitry in the second clock domain according to a control signal, the control signal being dependent on a phase difference between the first and the second clock signals.

15. The method of claim 14, wherein the at least two data signals include data signals in different latency domains when the phase difference between the first and the second clock signals are in certain ranges, the method further comprising freezing the control signal to avoid a change in latency in an output to the circuitry in the second clock domain.

16. The method of claim 14, further comprising:

comparing the first and second clocks to generate a phase comparison signal dependent on a phase difference between the first and second clocks;

integrating the phase comparison signal to produce a phase comparator output signal; and

latching the phase comparator output signal.

17. The method of claim 14, including storing a plurality of skip values each corresponding to a respective one of a plurality of operating frequencies, and selecting one of the plurality of skip values corresponding to a current operating frequency for use in the selecting operation.

18. The method of claim 14, wherein the outputting operation includes:

latching in a first one of the at least two parallel data paths the at least one sampled output on a first edge of a third clock signal that is in a fixed phase relationship with the second clock signal; and

latching in a second one of the at least two parallel data paths the at least one sampled output on a second edge of the third clock signal, the second edge having an opposite direction of transition relative to the first edge.

19. The method of claim 18, wherein the third clock signal is in quadrature with the second clock signal and is duty-cycle corrected.

20. The method of claim 18, wherein the outputting operation further includes retiming a latched signal in one of the at least two parallel data paths.

21. The method of claim 18, wherein the at least one sampled output includes a first sampled output generated by latching the input data signal on a rising edge of the first clock signal and a second sampled output generated by latching the input data signal on a falling edge of the first clock signal, and wherein the outputting operation includes:

latching in a first one of the at least two parallel data paths the first sampled output on an edge of a third clock signal that is in a fixed phase relationship with the second clock signal; and

latching in a second one of the at least two parallel data paths the second sampled output on the edge of the third clock signal.

22. The method of claim 21, wherein the at least one sampled output further includes a third sampled output generated by latching the input data signal on a rising edge of a fourth clock signal in a fixed phase relationship with the first clock signal and a fourth sampled output generated by latching the input data signal on a falling edge of the fourth clock signal, and wherein the outputting operation further includes:

latching in a third one of the at least two parallel data paths the third sampled output on the edge of the third clock signal; and

latching in a fourth one of the at least two parallel data paths the fourth sampled output on the edge of the third clock signal.