System and method for analog-to-digital conversion

• US 7,289,052 B1
• Filed: 04/25/2006
• Issued: 10/30/2007
• Est. Priority Date: 04/25/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Atris, Youssef H., Braswell, Brandt, Garrity, Douglas A.
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US11/411,352
• Publication Number:
  US 20070247345A1
• Time in Patent Office: 553 Days
• Field of Search: 341/155, 341/122, 341/172, 341/144, 341/118, 341/120, 341/163, 341/161
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/1225 using time-division multiplexing
• CPC Class Codes: H03M 1/403 using switched capacitors

Abstract

A system and method for converting an analog signal to a digital signal is provided including a first circuit (22) having a signal range and an input for receiving a first signal, and a second circuit (24) having an input receiving the analog signal and a first output coupled to the input of the first circuit. The first circuit (22) includes an amplifier (28). The first circuit (22) samples the first signal and produces the digital signal from the first signal using the amplifier. A second output of the second circuit (24) is coupled to the amplifier (28). The second circuit (24) samples and scales the analog signal via the amplifier (28) to produce the first signal within the signal range and cancels an offset of the first signal. The system and method reduce power consumption and save device area.

Claims

1. A system for converting an analog signal to a digital signal, the system comprising:

an amplifier;

a first circuit coupled to said amplifier, said first circuit having a signal range and having an input configured to receive a first signal, said first circuit configured to sample said first signal and further configured to produce the digital signal from the first signal via said amplifier; and

a second circuit having an input and first and second outputs, said input of said second circuit configured to receive the analog signal, said first output of said second circuit coupled to said input of said first circuit, said second output of said second circuit coupled to said amplifier, said second circuit configured to;

sample and scale the analog signal via said amplifier to produce said first signal within said signal range; and

cancel an offset of said first signal.

2. A system according to claim 1, wherein said first circuit is further configured to:

produce at least one sampled signal from said first signal;

sample a reference potential while producing said at least one sampled signal; and

apply a gain to said at least one sampled signal via said amplifier, said gain based on said reference potential.

3. A system according to claim 1, wherein said first circuit comprises a gain two plus/minus reference potential circuit.

4. A system according to claim 1, wherein said amplifier has an input and an output, and wherein said first circuit comprises:

a first switched capacitor network having first and second inputs and having an output coupled to said input of said amplifier, said first input of said first switched capacitor network coupled to said input of said first circuit and said output of said amplifier, said second input of said first switched capacitor network configured to receive a first reference potential, said first switched capacitor network configured to sample one of said first signal and a second signal at said first input of said first switched capacitor network and further configured to produce via said amplifier a third signal from a first combination of said first reference potential and one of said first and second signals; and

a second switched capacitor network having first and second inputs and having an output coupled to said input of said amplifier, said first input of said second switched capacitor network coupled to said output of said amplifier, said second input of said second switched capacitor network configured to receive a second reference potential, said second switched capacitor network configured to sample said third signal and further configured to produce via said amplifier said second signal from a second combination of said second reference potential and said third signal.

5. A system according to claim 1 further comprising a controller coupled to said first and second circuits, said controller configured to:

transmit a first control signal to said second circuit to produce said first signal; and

transmit a second control signal to said first circuit to sample at least one derivative signal based on said first signal.

6. A system according to claim 1, wherein said amplifier has an input and an output, and wherein said first circuit comprises:

a first switched capacitor network having an input and having an output coupled to said input of said amplifier, said input of said first switched capacitor network coupled to said input of said first circuit and said output of said amplifier, said first switched capacitor network configured to sample one of said first signal and a second signal and further configured to produce via said amplifier a third signal from a first combination of a first gain potential and one of said first and second signals;

a second switched capacitor network having an input coupled to a first reference potential and having an output coupled to said output of said first switched capacitor network, said second switched capacitor network configured to sample said first reference potential to produce said first gain potential;

a third switched capacitor network having first and second inputs and having an output coupled to said input of said amplifier, said first input of said third switched capacitor network coupled to said output of said amplifier, said second input of said third switched capacitor network coupled to said input of said first switched capacitor network, said second switched capacitor network configured to sample said third signal and further configured to produce via said amplifier said second signal from a second combination of said third signal and a second gain potential; and

a fourth switched capacitor network having an input coupled to a second reference potential and having an output coupled to said output of said third switched capacitor network, said fourth switched capacitor network configured to sample said second reference potential to produce said second gain potential.

7. A system according to claim 6 further comprising a comparator coupled to said first circuit, said comparator configured to:

determine a most significant bit (MSB) from said first signal;

transmit a first control signal to said second switched capacitor network to produce said first gain potential when said first switched capacitor network samples said first signal, said first control signal based on said MSB;

perform a first comparison of said third signal with a first predetermined value;

transmit a second control signal to said fourth switched capacitor network to produce said second gain potential when said third switched capacitor network samples said third signal, said second control signal based on said first comparison;

perform a second comparison of said second signal with a second predetermined value; and

transmit a third control signal to said second switched capacitor network to produce said first gain potential when said first switch capacitor network samples said second signal, said third control signal based on said second comparison, each of said first and second gain potentials representing one of a gain by two, a gain by two plus a predetermined potential, and a gain by two minus a predetermined potential.

8. A system for converting an analog signal to a digital signal, the system comprising:

a first circuit having a first input configured to receive a first signal and having a second input configured to receive a reference signal, said first signal having a signal range, said first circuit comprising an amplifier having an input and an output, said first circuit configured to produce the digital signal from said first signal and said reference signal;

a second circuit having first and second inputs and first and second outputs, said first input of said second circuit configured to couple to a first reference potential, said second input of said second circuit coupled to said output of said amplifier, said first output of said second circuit coupled to said second input of said first circuit, said second output of said second circuit coupled to said input of said amplifier, said second circuit configured to produce said reference signal via said amplifier from said first reference potential while canceling an offset of said reference signal; and

a third circuit having an input and first and second outputs, said input of said third circuit configured to receive the analog signal, said first output of said third circuit coupled to said first input of said first circuit, said second output of said third circuit coupled to said input of said amplifier, said second circuit configured to sample and scale the analog signal via said amplifier to produce said first signal within said signal range while canceling an offset of said first signal.

9. A system according to claim 8 further comprising a controller coupled to said first, second, and third circuits and configured to:

transmit a first control signal to said third circuit to produce said first signal;

transmit a second control signal to said second circuit to produce said reference signal; and

transmit a third control signal to said first circuit to sample said first signal while said second circuit produces said reference signal.

10. A system according to claim 8, wherein said first circuit comprises:

a first switched capacitor network having first and second inputs and having an output coupled to said input of said amplifier, said first input of said first switched capacitor network coupled to said first input of said first circuit and said output of said amplifier, said second input of said first switched capacitor network coupled to said second input of said first circuit, said first switched capacitor network configured to sample one of said first signal and a second signal at said first input of said first switched capacitor network and further configured to produce via said amplifier a third signal from a first combination of said reference signal and one of said first and second signals; and

a second switched capacitor network having first and second inputs and having an output coupled to said input of said amplifier, said first input of said second switched capacitor network coupled to said output of said amplifier, said second input of said second switched capacitor network coupled to said second input of said first circuit, said second switched capacitor network configured to sample said third signal and further configured to produce via said amplifier said second signal from a second combination of said reference signal and said third signal.

11. A system according to claim 10 further comprising a comparator coupled to said first circuit, said comparator configured to:

perform a first comparison with a sample of said first signal to determine an MSB;

transmit a first control signal to said first switched capacitor network, said first control signal directing said first switched capacitor network to apply a first gain to said sample of said first signal, said first gain derived from said reference signal and based on said first comparison;

perform a second comparison with a sample of said third signal to determine a first subsequent bit;

transmit a second control signal to said second switched capacitor network, said second control signal directing said second switched capacitor network to apply a second gain to said sample of said third signal, said second gain derived from said reference signal and based on said second comparison;

perform a third comparison with a sample of said second signal to determine a second subsequent bit; and

transmit a third control signal to said first switched capacitor network to apply a third gain to said sample of said second signal, said third gain derived from said reference signal and based on said third comparison.

12. A system according to claim 8, wherein said third circuit comprises:

a first switched capacitor network having an input coupled to said input of said third circuit and to a second reference potential and having an output coupled to said input of said amplifier, said first switched capacitor network configured to;

produce a sampled signal from the analog signal; and

scale said sampled signal to produce said first signal; and

a second switched capacitor network having an input coupled to said input of said amplifier and having an output coupled to said output of said amplifier, said second switched capacitor network configured to cancel offset of said first signal.

13. A method for converting an analog signal to a digital signal, the method comprising the steps of:

sampling and scaling the analog signal via an OPAMP to produce a first signal while canceling an offset of the first signal, the offset produced by the OPAMP; and

determining one or more bits of the digital signal by deriving one or more sampled signals from the first signal while applying a corresponding gain via the OPAMP to each of the one or more sampled signals, the corresponding gain based on a corresponding bit of the one or more bits of the digital signal.

14. A method according to claim 13, wherein said step of determining comprises:

sampling the first signal to produce a first sampled signal and determining an MSB of the first sampled signal while sampling a reference signal to produce a first gain, the first gain based on the MSB; and

applying the first gain to the first sampled signal via the OPAMP to produce a second signal.

15. A method according to claim 14, wherein said determining step comprises:

sampling the second signal to produce a second sampled signal while determining a first subsequent bit of the predetermined number of subsequent bits and sampling the reference signal to produce a second gain, the second gain based on the first subsequent bit;

applying the second gain to the second sampled signal via the OPAMP to produce a third signal;

sampling the third signal to produce a third sampled signal while determining a second subsequent bit of the predetermined number of subsequent bits and sampling the reference signal to produce a third gain, the third gain based on the second subsequent bit; and

applying the third gain to the third sampled signal via the OPAMP to produce a fourth signal.

16. A method according to claim 15, wherein said step of sampling the first signal comprises selecting the first gain from one of a group consisting of a gain by two, a gain by two plus a predetermined potential, and a gain by two minus a predetermined potential;

and

wherein each of said step of sampling the second signal and said step of sampling the third signal comprises selecting each of the second and third gains from one of the group consisting of a gain by two, a gain by two plus a predetermined potential, and a gain by two minus the predetermined potential.

17. A method according to claim 13 further comprising:

generating a reference signal via the OPAMP while canceling an offset in the reference signal produced by the OPAMP; and

producing the corresponding gain from the reference signal.

18. A method according to claim 13, wherein said step of determining comprises double-sampling at least one second signal, the at least one second signal derived from the first signal.

19. A method according to claim 13, wherein said step of sampling comprises:

sampling a reference potential; and

supplying a combination of a sample of the analog signal with the reference potential to the OPAMP.

20. A method according to claim 13, wherein said step of determining comprises:

determining a first bit of the one or more bits based on a first sampled signal of the one or more sampled signals;

determining a first potential based on the first bit of the one or more bits; and

supplying a combination of the first sampled signal of the one or more sampled signals with the first potential to the OPAMP, the corresponding gain based on the combination of the first sampled signal of the one or more sampled signals with the first potential to the OPAMP.