System and method for optically interconnecting memory devices

• US 7,289,347 B2
• Filed: 02/18/2005
• Issued: 10/30/2007
• Est. Priority Date: 08/02/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Taylor, George R.
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/062,075
• Publication Number:
  US 20050146946A1
• Time in Patent Office: 984 Days
• Field of Search: 365/64, 365/63, 365/215, 365/234, 365/109, 359/107
• US Class Current: 365/64
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1054 Optical output buffers
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1081 Optical input buffers
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.

Claims

1. A memory module, comprising:

an insulative substrate;

a plurality of memory devices mounted on the substrate, each memory device comprising;

a semiconductor substrate;

a plurality of electrical input and output signal lines fabricated in the semiconductor substrate including electrical data signal lines operable to output electrical read data signals and input electrical write data signals, and electrical address and control signal lines operable to input electrical address and control signals;

a plurality of optical receivers fabricated in the semiconductor substrate coupled to corresponding data, control and address signal lines, the receivers being operable to receive optical signals and develop corresponding electrical signals; and

a plurality of vertical cavity surface emitting lasers fabricated in the semiconductor substrate coupled to corresponding data signal lines, the vertical cavity surface emitting lasers being operable to receive electrical read data signals and develop corresponding optical read data signals;

a memory hub mounted on the insulative substrate, the memory hub having an input/output port and a plurality of input and output terminals including terminals outputting optical write data signals, terminals inputting optical read data signals, and terminals outputting optical command and address signals, the memory hub being operable to receive input signals coupled to the input/output port and to apply corresponding optical signals to the terminals of the memory hub, the memory hub being further operable to receive optical signals at the terminals of the memory hub and to apply output signals to the input/output port; and

a plurality of optical paths coupling the terminals of the memory hub to the vertical cavity surface emitting lasers and the optical receivers of the memory devices.

2. The memory module of claim 1 wherein the input/output port is operable to receive optical input signals, and transmit optical output signals.

3. The memory module of claim 2 wherein the optical input signals, comprise control, address and write data signals, and the optical output signals comprise read data signals.

4. The memory module of claim 1 wherein the input/output port is operable to receive electrical input signals, and transmit electrical output signals.

5. The memory module of claim 4 wherein the electrical input signals, comprise control, address and write data signals, and the electrical output signals comprise read data signals.

6. The memory module of claim 1 wherein the memory devices comprise dynamic random access memory devices.

7. The memory module of claim 1 wherein the optical receivers comprise optical Darlington transistors.

8. The memory module of claim 1 wherein the optical receivers comprise optical field effect transistors operable to receive optical signals.

9. The memory module of claim 1 wherein each optical path comprises a plurality of optical links.

10. The memory module of claim 1 wherein each optical path comprises a fiber optic link.

11. The memory module of claim 1 wherein each optical path comprises free space.

12. The memory module of claim 1 wherein each optical path comprises control, address and data busses.

13. The memory module of claim 1 wherein the optical paths are fabricated in the insulative substrate.

14. The memory module of claim 1 wherein the memory hub applies optical hub control, address and data signals to each memory device on the module simultaneously.

15. The memory module of claim 1 wherein the memory hub detects device address information in the input signal and applies optical control, address and data signals to a corresponding memory device on the module.

16. The memory module of claim 1 wherein the insulative substrate comprises a plurality of optical paths embedded within the insulative substrate.

17. A computer system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and data output devices;

a insulative substrate;

a controller coupled to the substrate and electrically coupled to the processor, the controller being operable to receive optical data signals and apply optical control, address and data signals to an optical path at a controller port;

a plurality of memory devices mounted on the substrate, each memory device comprising;

a semiconductor substrate;

a plurality of electrical input and output signal lines fabricated in the semiconductor substrate including electrical data signal lines operable to output electrical read data signals and input electrical write data signals; and

electrical address and control signal lines operable to input electrical address and control signals;

a plurality of optical receivers fabricated in the semiconductor substrate coupled to corresponding data, control and address signal lines, the receivers being operable to receive optical signals and generate corresponding electrical signals; and

a plurality of vertical cavity surface emitting lasers fabricated in the semiconductor substrate coupled to corresponding data signal lines, the vertical cavity surface emitting lasers being operable to receive electrical read data signals and generate corresponding optical read data signals;

a memory hub mounted on the insulative substrate, the memory hub having an input/output port and a plurality of input and output terminals including terminals outputting optical write data signals, command signals and address signals, and terminals inputting optical read data signals, the memory hub being operable to receive input signals coupled to the input/output port and to apply corresponding optical signals to the terminals of the memory hub, the memory hub being further operable to receive optical signals at the terminals of the memory hub and to apply output signals to the input/output port; and

a plurality of optical paths coupling the terminals of the memory hub to the vertical cavity surface emitting lasers and the optical receivers of the memory devices.

18. The computer system of claim 17 wherein the optical paths are embedded within the insulative substrate.

19. The computer system of claim 17 wherein the input/output port is operable to receive optical input signals, and transmit optical output signals.

20. The computer system of claim 19 wherein the optical input signals, comprise control, address and write data signals, and the optical output signals comprise read data signals.

21. The computer system of claim 17 wherein the input/output port is operable to receive electrical input signals, and transmit electrical output signals.

22. The computer system of claim 21 wherein the electrical input signals, comprise control, address and write data signals, and the electrical output signals comprise read data signals.

23. The computer system of claim 17 wherein the memory devices comprise dynamic random access memory devices.

24. The computer system of claim 17 wherein the optical receivers comprise optical Darlington transistors.

25. The computer system of claim 17 wherein the optical receivers comprise optical field effect transistors operable to receive optical signals.

26. The computer system of claim 17 wherein each optical path comprises a plurality of optical links.

27. The computer system of claim 17 wherein each optical path comprises a fiber optic link.

28. The computer system of claim 17 wherein each optical path comprises free space.

29. The computer system of claim 17 wherein each optical path comprises control, address and data busses.

30. The computer system of claim 17 wherein the memory hub is operable to apply optical hub control, address and data signals to each memory device on the module simultaneously.

31. The computer system of claim 17 wherein the memory hub is operable to detect device address information in the input signal and apply optical control, address and data signals to a corresponding memory device on the module.