Fast magnetic memory devices utilizing spin transfer and magnetic elements used therein

• US 7,289,356 B2
• Filed: 06/08/2005
• Issued: 10/30/2007
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Huai, Yiming, Diao, Zhitao, Pakala, Mahendra, Qian, Zhenghong
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/147,944
• Publication Number:
  US 20060279981A1
• Time in Patent Office: 874 Days
• Field of Search: 365/158, 365/173
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of magnetic storage cells includes a plurality of magnetic elements and at least one selection transistor. Each of the plurality of magnetic elements is capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element. Each of the plurality of magnetic elements has a first end and a second end. The at least one selection transistor is coupled to the first end of each of the plurality of magnetic elements. The plurality of word lines is coupled with the plurality of selection transistors and selectively enables a portion of the plurality of selection transistors.

Claims

1. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements, the plurality of magnetic elements including at least a first magnetic element and a second magnetic element;

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors;

a plurality of bit lines;

a plurality of bit line selection transistors coupled with the plurality of bit lines, for selectively enabling a portion of the plurality of bit lines; and

a plurality of data lines for each of the plurality of magnetic storage cells, a first data line of the plurality of data lines coupled with the second end of the first magnetic element and a second data line of the plurality of data lines coupled with the second end of the second magnetic element, the plurality of data lines for providing a write current during writing and a sense current during reading of the plurality of magnetic storage cells.

2. The magnetic memory of claim 1 wherein the plurality of magnetic storage cells are organized into pairs including a first magnetic storage cell and a second magnetic storage cell, wherein the selection transistor of the first magnetic storage cell and the selection transistor of the second magnetic storage cell share a drain.

3. The magnetic memory of claim 1 wherein the plurality of bit lines include a plurality of subsidiary bit lines, each of the subsidiary bit lines coupled with a portion of the plurality of magnetic elements, the plurality of bit line selection transistors corresponding to the plurality of subsidiary bit lines.

4. The magnetic memory of claim 3 wherein the plurality of data lines include a plurality of subsidiary data lines, the plurality of subsidiary data lines including the first data line and the second data line for a portion of the plurality of magnetic storage cells.

5. The magnetic memory of claim 1 wherein the first data line is coupled to ground.

6. The magnetic memory of claim 5 wherein the plurality of bit lines are coupled to a plurality of differential sense amplifiers.

7. The magnetic memory of claim 5 wherein each of the plurality of bit lines are coupled to each of a plurality of differential sense amplifiers.

8. The magnetic memory of claim 1 wherein the plurality of bit lines are coupled with at least one current converting circuit.

9. The magnetic element of claim 1 wherein the first data line is a separate data line for each of the plurality of magnetic storage cells and wherein the second data line is a common data line for a portion of the plurality of magnetic storage cells.

10. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements; and

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors;

a plurality of bit lines;

wherein the plurality of magnetic elements include a first magnetic element and a second magnetic element and wherein the at least one selection transistor includes a single selection transistor; and

wherein the first magnetic element includes a first storage layer having a first magnetization and the second magnetic element includes a second storage layer having a second storage layer, the first magnetization aligned substantially antiparallel with the second magnetization.

11. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements;

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

a plurality of bit lines

wherein a first magnetic element of the plurality of magnetic elements is disposed substantially directly above a second magnetic element of the plurality of magnetic elements; and

wherein each of the first magnetic element and the second magnetic element includes a tunneling magnetoresistive junction.

12. The magnetic memory of claim 11 wherein the tunneling magnetoresistive junctions includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer residing between the pinned layer and the free layer.

13. The magnetic memory of claim 12 wherein the pinned layer is a synthetic pinned layer including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer.

14. The magnetic memory of claim 12 wherein the pinned layer of the first magnetoresistive storage element resides above the free layer of the first magnetoresistive storage element and wherein the pinned layer of the second magnetoresistive storage element resides below the free layer of the second magnetoresistive storage element.

15. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements;

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

a plurality of bit lines

wherein a first magnetic element of the plurality of magnetic elements is disposed substantially directly above a second magnetic element of the plurality of magnetic elements; and

wherein the first magnetoresistive storage element and the second magnetoresistive storage element each include a separate cell plate and are separated by an insulating layer.

16. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements;

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

a plurality of bit lines

wherein a first magnetic element of the plurality of magnetic elements is disposed substantially directly above a second magnetic element of the plurality of magnetic elements; and

wherein the first magnetoresistive storage element and the second magnetoresistive storage element each share a cell plate.

17. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements;

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

a plurality of bit lines;

at least one of wherein the plurality of magnetic elements include a plurality of dual tunneling magnetoresistive junctions, wherein each of the plurality of magnetic elements includes a first pinned layer, a tunneling barrier layer, a free layer, a nonmagnetic spacer layer, and a second pinned layer, the tunneling barrier layer residing between the free layer and the first pinned layer, the nonmagnetic spacer layer residing between the second pinned layer and the free layer, wherein each of the plurality of magnetic elements include a plurality of tunneling magnetoresistive junctions, each of the plurality of tunneling magnetoresistive junctions being separated by a nonmagnetic layer, wherein each of the plurality of magnetic elements include at least one tunneling magnetoresistive junction and at least one spin valve, each of the at least one tunneling magnetoresistive junction and the at least one spin valve being separated by a nonmagnetic spacer layer, wherein each of the plurality of magnetic elements includes a free layer, the free layer including an amorphous forming element having a concentration of not more than thirty atomic percent and at least one of Co, Fe, and Ni, wherein each of the plurality of magnetic elements includes a free layer, the free layer including an amorphous forming element and at least one of Co, Fe, and Ni, the amorphous forming element including boron, wherein each of the plurality of magnetic elements includes a free layer, the free layer including an amorphous forming element and at least one of Co, Fe, and Ni, the free layer having a saturation magnetization of between four hundred and one thousand five hundred emu/cm³, wherein each of the plurality of magnetic elements includes a free layer, the free layer including at least one of Co, Fe, and Ni and being a multilayer including a plurality of layers, wherein each of the plurality of magnetic elements includes a free layer and a pinned layer, each of the pinned layer and the free layer including at least one of Co, Fe, and Ni and the pinned layer is a multilayer including a plurality of layers, and wherein each of the plurality of magnetic elements includes a free layer, a pinned layer and at least one nonmagnetic spacer layer including at least one nano-oxide layer, each of the free layer and the pinned layer including at least one of Co, Fe, and Ni.

18. The magnetic memory of claim 17 wherein each of the plurality of dual tunneling magnetoresistive junctions includes a synthetic pinned layer including a first magnetic layer, a second magnetic layer, and a nonmagnetic spacer layer between the first magnetic layer and the second magnetic layer.

19. The magnetic memory of claim 17 wherein the first pinned layer is a synthetic pinned layer including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer.

20. The magnetic memory of claim 17 wherein the plurality of layers include a plurality of ferromagnetic layers.

21. The magnetic memory of claim 20 wherein the plurality of ferromagnetic layers includes at least one of Co, CoFe with 5-40 atomic percent Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B, CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe with approximately 20 atomic percent Fe, CoPt with 5-40 atomic percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic percent Pt, Co₂MnAl, Co₂MnSi, or Co₂CrAl, Co₂CrSi, Co₂FeAl and Co₂FeSi.

22. The magnetic memory of claim 20 wherein the plurality of layers include at least one nonmagnetic layer separating a portion of the plurality of ferromagnetic layers.

23. The magnetic memory of claim 22 wherein the ferromagnetic material includes at least one of Co, CoFe with 5-40 atomic percent Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B, CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe with approximately 20 atomic percent Fe, CoPt with 5-40 atomic percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic percent Pt, Co₂MnAl, Co₂MnSi, or Co₂CrAl, Co₂CrSi, Co₂FeAl and Co₂FeSi.

24. The magnetic memory of claim 22 wherein the nonmagnetic layer includes at least one of Ru, Rh, Re, Cr and Cu.

25. The magnetic memory of claim 17 wherein the plurality of layers include a plurality of ferromagnetic layers.

26. The magnetic memory of claim 25 wherein the plurality of ferromagnetic layers includes at least one of Co, CoFe with 5-40 atomic percent Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B, CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe with approximately 20 atomic percent Fe, CoPt with 5-40 atomic percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic percent Pt, Co₂MnAl, Co₂MnSi, or Co₂CrAl, Co₂CrSi, Co₂FeAl and Co₂FeSi.

27. The magnetic memory of claim 25 wherein the plurality of layers include at least one nonmagnetic layer separating a portion of the plurality of ferromagnetic layers.

28. The magnetic memory of claim 27 wherein the ferromagnetic material includes at least one of Co, CoFe with 5-40 atomic percent Fe, CoFeB with 5-40 atomic percent Fe and 5-30 atomic percent B, CoFeTa with 5-40 atomic percent Fe and 5-30 atomic percent Ta, NiFe with approximately 20 atomic percent Fe, CoPt with 5-40 atomic percent Pt, CoPd with 5-40 atomic percent Pd, FePt with 5-40 atomic percent Pt, Co₂MnAl, Co₂MnSi, or Co₂CrAl, Co₂CrSi, Co₂FeAl and Co₂FeSi.

29. The magnetic memory of claim 27 wherein the nonmagnetic layer includes at least one of Ru, Re, and Cu.

30. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements;

a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

a plurality of bit lines;

wherein each of the plurality of magnetic elements includes a free layer, the free layer including at least one of Co, Fe, and Ni;

wherein each of the plurality of magnetic elements includes a pinned layer including at least one of Co, Fe, and Ni; and

wherein each of the plurality of magnetic elements includes at least one tunneling barrier layer.

31. The magnetic memory of claim 30 wherein the at least one tunneling barrier layer includes at least one of AlO with 40-70 atomic percent O, MgO with 30-60 atomic percent O, and AlON with 40-70 atomic percent O and 2-30 atomic percent N, AlN with 30-60 atomic percent N, AlZrO, AlHfO, AlTiO, and AlTaO.

32. The magnetic memory of claim 30 wherein the at least one tunneling barrier layer includes a plurality of layers.

33. The magnetic memory of claim 30 wherein the at least one tunneling barrier layer has a thickness of at least five Angstroms and not more than forty Angstroms.

34. The magnetic memory of claim 30 wherein the at least one tunneling barrier layer has a resistance-area product between ten and one hundred Ω

-μ

m².

35. A method for providing a magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements, the magnetic storage cell providing further including providing a first magnetic element and a second magnetic element and wherein the at least one selection transistor includes a single selection transistor;

providing a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors;

providing a plurality of bit lines;

providing a plurality of bit line selection transistors coupled with the plurality of bit lines, for selectively enabling a portion of the plurality of bit lines; and

providing a plurality of data lines for each of the plurality of magnetic storage cells, a first data line of the plurality of data lines coupled with the second end of the first magnetic element and a second data line of the plurality of data lines coupled with the second end of the second magnetic element, the plurality of data lines for providing a write current during writing and a sense current during reading of the plurality of magnetic storage cells.

36. The method of claim 35 wherein providing the plurality of magnetic storage cells includes:

organizing the plurality of magnetic storage cells into pairs including a first magnetic storage cell and a second magnetic storage cell, the selection transistor of the first magnetic storage cell and the selection transistor of the second magnetic storage cell sharing a drain.

37. The method of claim 35 wherein providing the plurality of bit lines includes:

providing a plurality of subsidiary bit lines, each of the subsidiary bit lines coupled with a portion of the plurality of magnetic elements, the plurality of bit line selection transistors corresponding to the plurality of subsidiary bit lines.

38. The method of claim 35 wherein providing the plurality of data lines further includes:

providing a plurality of subsidiary data lines, the plurality of subsidiary data lines including the first data line and the second data line for a portion of the plurality of magnetic storage cells.

39. The method of claim 35 wherein providing plurality of data lines includes:

coupling the first data line to ground.

40. The method of claim 39 wherein providing the plurality of bit lines further includes:

coupling the plurality of bit lines to a plurality of differential sense amplifiers.

41. The method of claim 39 wherein each of the plurality of bit lines are coupled to each of a plurality of differential sense amplifiers.

42. The method of claim 35 further comprising:

coupling the plurality of bit lines with at least one current converting circuit.

43. The method element of claim 35 wherein the first data line is a separate data line for each of the plurality of magnetic storage cells and wherein the second data line is a common data line for a portion of the plurality of magnetic storage cells.

44. A method for providing a magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements, the magnetic storage cell providing further including providing a first magnetic element and a second magnetic element and wherein the at least one selection transistor includes a single selection transistor;

providing a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

providing a plurality of bit lines;

wherein providing the plurality of magnetic storage cells further includes;

providing the first magnetic element including a first storage layer having a first magnetization; and

providing the second magnetic element including a second storage layer having a second storage layer, the first magnetization aligned substantially antiparallel with the second magnetization.

45. A method for providing a magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements, wherein providing the plurality of magnetic storage cells further includes providing a first magnetic element of the plurality of magnetic elements is disposed substantially directly above a second magnetic element of the plurality of magnetic elements;

providing a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

providing a plurality of bit lines;

at least one of wherein each of the first magnetic element and the second magnetic element includes a tunneling magnetoresistive junctions;

wherein the first magnetoresistive storage element and the second magnetoresistive storage element each include a separate cell plate and are separated by an insulating layer.

46. The method of claim 45 wherein the tunneling magnetoresistive junctions includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer residing between the pinned layer and the free layer.

47. The method of claim 46 wherein the pinned layer is a synthetic pinned layer including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer.

48. The method of claim 47 wherein the pinned layer of the first magnetoresistive storage element resides above the free layer of the first magnetoresistive storage element and wherein the pinned layer of the second magnetoresistive storage element resides below the free layer of the second magnetoresistive storage element.

49. A method for providing a magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a plurality of magnetic elements capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, each of the plurality of magnetic elements having a first end and a second end, and at least one selection transistor coupled to the first end of each of the plurality of magnetic elements;

providing a plurality of word lines coupled with the plurality of selection transistors and for selectively enabling a portion of the plurality of selection transistors; and

providing a plurality of bit lines;

wherein the plurality of magnetic elements includes at least one of providing a plurality of dual tunneling magnetoresistive junctions;

providing a first pinned layer, a tunneling barrier layer, a free layer, a nonmagnetic spacer layer, and a second pinned layer for each of the plurality of magnetic elements, the tunneling barrier layer residing between the free layer and the first pinned layer, the nonmagnetic spacer layer residing between the second pinned layer and the free layer;

providing a plurality of tunneling magnetoresistive junctions for each or the plurality of magnetic storage cells, each of the plurality of tunneling magnetoresistive junctions being separated by a nonmagnetic layer; and

providing at least one tunneling magnetoresistive junction and at least one spin valve, each of the at least one tunneling magnetoresistive junction and the at least one spin valve being separated by a nonmagnetic spacer layer.