Multi-state memory

• US 7,289,360 B2
• Filed: 01/11/2006
• Issued: 10/30/2007
• Est. Priority Date: 08/07/1997
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/330,923
• Publication Number:
  US 20060129751A1
• Time in Patent Office: 657 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.21, 365/189.07, 365/189.09, 365/185.22, 365/210
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1. A non-volatile memory, comprising:

a memory array having one or more memory cells each capable of storing N bits of data, where N is greater than or equal to two; and

read circuitry connectable to the memory array, including one or more sense circuits each connectable to one or more of the memory cells, each of the sense circuits including;

a sense amp to determine the response of a corresponding memory cell to a read voltage applied thereto;

voltage application circuitry to apply a plurality of current values for the read voltage to a terminal of the corresponding memory cell, the voltage application circuitry including circuitry to determine the current read voltage value based on output of said sense amp in response to a preceding read voltage value; and

register circuitry to store the response of the corresponding memory cell to at least N of said read voltage values.

2. The memory of claim 1, wherein the plurality of read voltage values includes an initial read voltage level and at least (N−

1) additional read voltage levels.

3. The memory of claim 2, wherein the initial read voltage is used to determine the most significant bit of the data stored on each of said selected memory cells, and each subsequent read voltage level is used to determine the next most significant bit of the data stored on each of said selected memory cells.

4. The memory of claim 1, wherein the current value for the read voltage is either greater than or less than the preceding read voltage value based on output of said sense amp in response to the preceding read voltage value.

5. The memory of claim 1, wherein said one or more of the memory cells is a plurality of memory cells to be read concurrently and the read circuitry includes a corresponding plurality of sense circuits, wherein each of the corresponding plurality sense circuits determines the corresponding current read voltage value independently of the other ones of the plurality sense circuits.

6. The memory of claim 5, wherein the number of said plurality of memory cells to be read concurrently corresponds the physical unit of read of the memory, the physical unit of read being the number of physical cells that memory is able to sense simultaneously.

7. The memory of claim 1, wherein said sense amps determine the response of a corresponding memory cell to a read voltage applied thereto by comparing the current though the selected cells to one or more reference currents.

8. The memory of claim 1, wherein the number of said plurality of values for the read voltage is a number greater than N.

9. The memory of claim 1, wherein the memory cells are charge storing devices.

10. The memory of claim 9, wherein the memory array is a flash memory.

11. The memory of claim 9, wherein the terminal of the corresponding memory cell is a control gate.