Systems and methods for wireless communication over a wide bandwidth channel using a plurality of sub-channels

• US 7,289,494 B2
• Filed: 12/06/2001
• Issued: 10/30/2007
• Est. Priority Date: 12/06/2001
• Status: Expired due to Fees

• Current Assignee: Intellectual Ventures Holding 73 LLC (Intellectual Ventures LLC), Wideband Access, Inc.
• Original Assignee: Pulse-Link Incorporated
• Inventors: Lakkis, Ismail Adnan
• Primary Examiner(s): NGUYEN, HANH N
• Application Number:
  US10/010,601
• Publication Number:
  US 20050201326A1
• Time in Patent Office: 2,154 Days
• Field of Search: 370/330, 370/478, 370/343, 370/336, 370/345, 370/328, 370/329, 370/480, 370/481, 370/366, 370/314, 455/450, 455/451, 455/452, 375/260
• US Class Current: 370/366
• CPC Class Codes: H04B 1/71632 Signal aspects H04B1/7172 and H04B1/7176 take precedence
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence

Abstract

A method of communicating over a wideband communication channel divided into a plurality of sub-channels comprises dividing a single serial message intended for one of the plurality of communication devices into a plurality of parallel messages, encoding each of the plurality of parallel messages onto at least some of the plurality of sub-channels, and transmitting the encoded plurality of parallel messages to the communication device over the wideband communication channel.

Claims

1. A transmitter, comprising

a serial-to-parallel transmitter structured to transform a single serial bit stream comprising messages for a plurality of communication devices into a plurality of bit streams;

a time division modulator structured to perform time division modulation on each of the plurality of bit streams;

a filter structured to apply a required pulse shaping to each of the plurality of bit streams;

a frequency shifter structured to shift each of the plurality of bit streams in frequency by a required amount; and

a summer structured to sum the plurality of bit streams into a single transmit signal;

wherein the time division modulator comprises, for each bit stream;

a sub-block repeater structured to take a sub-block of data from the bit stream and form a new sub-block comprising the original sub-block repeated two or more times;

a block terminator structured to add a termination prefix to the new sub-block; and

a sync inserter structured to periodically insert a synchronization code into the bit streams.

2. The transmitter of claim 1, wherein the time division modulator further comprises for each bit stream a sub-block scrambler structured to scramble the new sub-block generated by the sub-block repeater.

3. The transmitter of claim 2, wherein the time division modulator further comprises for each bit stream a block repeater structured to generate another new sub-block comprising the terminated new sub-block repeated two or more times.

4. The transmitter of claim 3, wherein the block repeater is further structured to scramble the new sub-block that it generates.

5. The transmitter of claim 1, wherein the block terminator is structured to perform block termination using a cyclic prefix or a known sequence prefix.

6. A transmitter, comprising:

a serial-to-parallel transformer structured to transform a single serial bit stream comprising messages for a plurality of communication devices into a plurality of bit streams;

a frequency division modulator structured to perform frequency division modulation an each of the plurality of bit streams,

a filter structured to apply a required pulse shaping to each of the plurality of bit streams;

a frequency shifter structured to shift each of the plurality of bit streams in frequency by a required amount; and

a summer structured to sum the plurality of bit streams into a single transmit signal;

wherein the frequency division modulator comprises, for each bit stream;

a sub-block repeater structured to take a sub-block of data from the bit stream and form a new sub-block comprising the original sub-block repeated twice;

a block terminator structured to add a cyclic termination prefix to the new sub-block; and

a sync inserter structured to periodically insert a synchronization code into the bit stream.

7. The transmitter of claim 6, wherein the frequency division modulator further comprises for each bit stream a sub-block scrambler structured to scramble the new sub-block generated by the sub-block repeater.

8. The transmitter of claim 7, further comprising for each bit stream a block coder structured to code the scrambled new sub-block.

9. The transmitter of claim 8, further comprising for each bit stream an inverse transformer structured to generate a transformed sub-block comprising the inverse fast fourier transform of the coded new sub-block, and wherein the block terminator is structured to add a cyclic termination prefix to the transformed sub-block.

10. The transmitter of claim 9, wherein the sub-block repeater, sub-block scrambler, block coder, and inverse transmitter are structured to be turned on and off as required.