Method and system for embedding wire model objects in a circuit schematic design

• US 7,290,235 B2
• Filed: 09/22/2005
• Issued: 10/30/2007
• Est. Priority Date: 09/22/2005
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Heymann, Omer, Leibowitz, Moshe, Noy, Gil, Goren, Lidor, Amit, Niv, Speiser, Maya, Bustin, Ronit, Raphayevich, Alex
• Primary Examiner(s): Lin; Sun James
• Application Number:
  US11/232,745
• Publication Number:
  US 20070067749A1
• Time in Patent Office: 768 Days
• Field of Search: 716/12, 716/11, 716/5, 716/6
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Claims

1. A method for schematically embedding wire model objects (WMOs) into a schematic design of an integrated circuit, comprising:

a) estimating a wiring routing geometry for each signal path in said integrated circuit and associating a signal path name to a respective estimated wiring routing geometry;

b) selecting one or more cascading WMOs for each segment in each estimated wiring routing geometry and associatively coupling said one or more cascading WMOs to one another and to source and target points of the respective signal path name; and

c) substituting each signal path with said one or more cascading WMOs.

2. The method according to claim 1, comprising deriving, from a first schematic file relating to logical connections in the integrated circuit and to physical size of components of said integrated circuit, and from placement data relating to physical locations of said components, a second schematic file in which wire model objects are substituted for signal paths.

3. The method according to claim 2, wherein a second schematic design in the second schematic file is displayable on a computer display.

4. The method according to claim 3, wherein each signal path of interest in the second schematic design is traceable by navigating from one circuit'"'"'snode to another by using, clicking, or touching displayed connection labels associated with said each signal path.

5. The method according to claim 4, wherein discrete elements of the WMOs associated with the signal path of interest are displayable.

6. The method according to claim 4, wherein the WMOs associated with the signal path of interest are displayable as symbols.

7. The method according to claim 1, wherein associatively coupling said one or more cascading WMOs comprises using connection labels, wherein input/output terminals in the integrated circuit and terminals of the wire model objects belonging to the same circuit node are assigned a common connection label to logically interconnect said input/output terminals.

8. The method according to claim 1, wherein the estimated wiring routing geometry further comprises via connections, and a corresponding WMO is selected for each of said via connections.

9. A computer program product for schematically embedding wire model objects (WMOs) into a schematic design of an integrated circuit, comprising a computer useable medium that includes a computer readable program;

said computer readable program, when executed on a computer, causes said computer to;

estimate a wiring routing geometry for each signal path in said integrated circuit and associate a signal path name to a respective estimated wiring routing geometry;

select one or more cascading WMOs for each segment in each estimated wiring routing geometry and associatively couple said one or more cascading WMOs to one another and to source and target points of the respective signal path name; and

substitute each said signal path with said one or more cascading WMOs.

10. The computer program product according to claim 9, wherein associatively coupling said one or more cascading WMOs comprises using connection labels, wherein input/output terminals in the integrated circuit and terminals of the wire model objects belonging to the same circuit node are assigned a common connection label to logically interconnect said input/output terminals.

11. The computer program product according to claim 9, wherein said computer readable program, when executed on a computer, causes said computer to derive, from a first schematic file relating to logical connections in the integrated circuit and to physical size of components of said integrated circuit, and from placement data relating to physical locations of said component, a second schematic file in which wire model objects are substituted for signal paths.

12. A system for schematically embedding wire model objects (WMOs) into a schematic design of an integrated circuit, comprising:

a wire model embedder to estimate a wiring routing geometry for each signal path in said integrated circuit and associate a signal path name to a respective estimated wiring routing geometry;

to select one or more cascading WMOs for each segment in each estimated wiring routing geometry and associatively couple said one or more cascading WMOs to one another and to source and target points of the respective signal path name; and

to substitute each said signal path with said one or more cascading WMOs.

13. The system according to claim 12, wherein the wire model embedder derives from the schematic design file of the integrated circuit a second schematic design file wherein wire model objects are substituted for signal paths by schematically inserting said one or more cascading WMOs between components of said integrated circuit using common labels.

14. The system according to claim 12, comprising an input memory for storing therein a first schematic design flle including data relating to a physical geometry of wiring routing of essentially every signal path in the integrated circuit, and to original logical connectivity within the integrated circuit, said geometry being definable by a cluster consisting of one or more source and target points, and by line segments that interconnect these points.

15. The system according to claim 12, wherein the wire model embedder comprises:

a wire model renderer for estimating the wire routing geometries;

a model decision maker for selecting the WMOs each segment should be substituted with; and

a new connectivity generator for substituting the signal paths with respective WMOs, whereby to derive a second schematic design file.

16. The system according to claim 15, comprising an output memory for storing therein the resulting second schematic design file.

17. The system according to claim 12, wherein the associatively coupling said one or more cascading WMOs comprises using connection labels, wherein input/output terminals in the integrated circuit and terminals of the wire model objects belonging to the same circuit node are assigned a common connection label to logically interconnect said input/output terminals.

18. The system according to claim 12, wherein the estimated wiring routing geometry further comprises via connections, and a corresponding WMO is selected for each of said via connections.