MEMS device integrated chip package, and method of making same

• US 7,291,561 B2
• Filed: 07/21/2003
• Issued: 11/06/2007
• Est. Priority Date: 10/12/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ma, Qing, Rao, Valluri, Cheng, Peng
• Primary Examiner(s): Crane; Sara
• Assistant Examiner(s): Gebremariam; Samuel A.
• Application Number:
  US10/623,965
• Publication Number:
  US 20040016989A1
• Time in Patent Office: 1,569 Days
• Field of Search: 228/217, 228/221, 228/123.1, 428/1.38, 428/138, 257/528, 257/532, 257/303, 257/306, 257/777, 257/307, 257/308, 257/782, 438/691, 438/692, 438/695, 438/697
• US Class Current: 438/691
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: H01G 5/16 using variation of distance between electrodes
• CPC Class Codes: H01G 5/40 Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: Y10T 428/24248 One piece

Abstract

The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance.

The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Claims

1. A process of forming a micro electromechanical (MEMS) package comprising:

coupling a first MEMS device to an active surface of a semiconductor device using a first contact array;

providing a conveyance including a second MEMS device disposed therein and including a via extending through the entire thickness of the conveyance; and

supporting the conveyance over the active surface using a plurality of electrical contacts in a second contact array, wherein the second MEMS device communicates electrically to the semiconductor device via at least one of the contacts in the second contact array and wherein the first MEMS device is positioned within the via.

2. The process according to claim 1, wherein the second MEMS device is selected from a switch, a capacitor, an inductor, an oscillator, a power supply, and combinations thereof.

3. The process according to claim 1, further comprising:

providing a sealing structure on the semiconductor device; and

disposing the sealing structure in a manner sufficient to isolate the first MEMS device.

4. The process according to claim 1 further comprising:

forming an integrated package comprising the semiconductor device and the conveyance.

5. The process according to claim 4 further comprising:

encapsulating the first MEMS device and the conveyance to form an integrated package.

6. The process according to claim 1 further comprising:

encapsulating the semiconductor device to form an integrated package, wherein the first MEMS device is accommodated upon the semiconductor device.

7. A process comprising:

coupling a first MEMS device to an active surface of a semiconductor device using a first contact array;

providing a conveyance including a second MEMS device disposed therein and including a via extending through the entire thickness of the conveyance; and

supporting the conveyance over the active surface using a plurality of electrical contacts in a second contact array, wherein the second MEMS device communicates electrically to the semiconductor device via at least one of the contacts in the second contact array, and wherein the first MEMS device is positioned within the via; and

contacting encapsulation material with at least one of the semiconductor device, the first MEMS device, and the conveyance to form an integrated MEMS package.

8. The process according to claim 7, wherein the first MEMS device is selected from a switch, a capacitor, an inductor, an oscillator, a power supply, and combinations thereof.

9. The process according to claim 7, further comprising:

providing a sealing structure; and

interposing the sealing structure upon the semiconductor device in a manner sufficient to isolate the first MEMS device.