Trench MIS device having implanted drain-drift region and thick bottom oxide

• US 7,291,884 B2
• Filed: 06/04/2003
• Issued: 11/06/2007
• Est. Priority Date: 07/03/2001
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Qi, Jainhai, Terrill, Kyle W.
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US10/454,031
• Publication Number:
  US 20040038467A1
• Time in Patent Office: 1,616 Days
• Field of Search: 257/155, 257449-454, 257328-344, 257352-355, 257/345, 257/368, 438/270, 438/268, 438/269, 438/242
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The N-epitaxial layer increases the breakdown voltage of the MIS device. In alternative embodiments, the thick bottom oxide layer can be omitted.

Claims

1. A trench MIS device comprising:

a substrate of a first conductivity type;

a first epitaxial layer of the first conductivity type on the substrate, the first epitaxial layer being doped more lightly than the substrate;

a second epitaxial layer of a second conductivity type on the first epitaxial layer, a trench being formed in the second epitaxial layer, the trench having a bottom in the second epitaxial layer above an interface between the first and second epitaxial layers;

a gate in the trench;

a gate insulating layer along a sidewall of the trench, the gate being electrically insulated from the second epitaxial layer by the gate insulating layer;

a bottom insulating layer on the bottom of the trench, the bottom insulating layer being thicker than the gate insulating layer;

a drain-drift region of the first conductivity type extending between the bottom of the trench and the first epitaxial layer, the drain-drift region forming a PN junction with the second epitaxial layer, the PN junction extending between the trench and the first epitaxial layer, wherein the PN junction is aligned with an edge of the bottom insulating layer.

2. The trench MIS device of claim 1 wherein the drain-drift region does not extend downward to the substrate.

3. The trench MIS device of claim 1 further comprising a metal layer in electrical contact with a top surface of the second epitaxial layer.

4. The trench MIS device of claim 1 wherein the edge of the bottom insulating layer is located adjacent an area of contact between the bottom insulating layer and the gate insulating layer.