Phase locked loop frequency synthesizer
First Claim
1. A phase locked loop frequency synthesizer, comprising:
- an LC-tank circuit which includes an inductor and a variable capacitor in which a capacitance changes depending on an input voltage;
a group of fixed-value capacitors which are selectively connected to said LC-tank circuit in parallel;
a voltage controlled oscillating unit which outputs a signal with a frequency determined by said LC-tank circuit and said group of fixed-value capacitors;
a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of said frequency output from said voltage controlled oscillating unit;
a fixed-value capacitor controlling unit which outputs a selection signal which determines a combination of said fixed-value capacitors to be connected to said LC-tank circuit based on a frequency dividing ratio setting signal including information about a dividing ratio of said second signal, and controls the connection of said fixed-value capacitors selected from said group of fixed-value capacitors based on said selection signal; and
a variable capacitor controlling unit which selects either one of a fixed bias voltage and a voltage obtained by converting said output current output from said phase control unit and inputs the selected voltage to said variable capacitor of said LC-tank circuit,wherein said fixed-value capacitor controlling unit includes;
a first counter which counts said first signal;
a second counter which counts a count number of said second signal while said first counter counts predetermined numbers of said first signal;
a calculation unit that calculates an ideal value for said count number of said second signal while said predetermined numbers of said first signal is counted; and
a comparator which compares said count number counted by said second counter and said ideal value and outputs a differential operator thereof,said fixed-value capacitor controlling unit correcting said selection signal based on said differential operator.
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Abstract
The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connection of the fixed-value capacitors selected from the group of fixed-value capacitors based on the selection signal to the LC-tank circuit in parallel; and a variable capacitor controlling unit which selects either one of a fixed bias voltage and the voltage obtained by converting the output current output from the phase control unit and inputs the selected voltage to the variable capacitor of the LC-tank circuit.
18 Citations
18 Claims
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1. A phase locked loop frequency synthesizer, comprising:
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an LC-tank circuit which includes an inductor and a variable capacitor in which a capacitance changes depending on an input voltage; a group of fixed-value capacitors which are selectively connected to said LC-tank circuit in parallel; a voltage controlled oscillating unit which outputs a signal with a frequency determined by said LC-tank circuit and said group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of said frequency output from said voltage controlled oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines a combination of said fixed-value capacitors to be connected to said LC-tank circuit based on a frequency dividing ratio setting signal including information about a dividing ratio of said second signal, and controls the connection of said fixed-value capacitors selected from said group of fixed-value capacitors based on said selection signal; and a variable capacitor controlling unit which selects either one of a fixed bias voltage and a voltage obtained by converting said output current output from said phase control unit and inputs the selected voltage to said variable capacitor of said LC-tank circuit, wherein said fixed-value capacitor controlling unit includes; a first counter which counts said first signal; a second counter which counts a count number of said second signal while said first counter counts predetermined numbers of said first signal; a calculation unit that calculates an ideal value for said count number of said second signal while said predetermined numbers of said first signal is counted; and a comparator which compares said count number counted by said second counter and said ideal value and outputs a differential operator thereof, said fixed-value capacitor controlling unit correcting said selection signal based on said differential operator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A fixed-value capacitor controlling unit for a phase locked loop frequency synthesizer, said fixed-value capacitor controlling unit comprising:
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a first counter which counts a first signal representing a reference frequency; a second counter which counts, while said first counter counts predetermined numbers of said first signal, a second signal representing a frequency output by an oscillating unit of said phase locked loop frequency synthesizer; a calculation unit that calculates an ideal value for said count number of said second signal; and a comparator which compares said count number counted by said second counter and said ideal value to output a differential operator thereof, said fixed-value capacitor controlling unit providing, based on said differential operator, a selection signal which determines a combination of fixed-value capacitors to be connected to an LC-tank circuit of said phase locked loop frequency synthesizer. - View Dependent Claims (15, 16, 17)
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18. A phase locked loop frequency synthesizer, comprising:
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a fixed-value capacitor controlling unit comprising; a first counter which counts a first signal representing a reference frequency; a second counter which counts a second signal representing a frequency output by an oscillating unit of said phase locked loop frequency synthesizer; a calculation unit that calculates an ideal value for said count number of said second signal; and a comparator which compares said count number counted by said second counter and said ideal value to output a differential operator thereof, said fixed-value capacitor controlling unit correcting, based on said differential operator to output to voltage control oscillating, a selection signal which determines a combination of fixed-value capacitors to be connected to an LC-tank circuit of said phase locked loop frequency synthesizer.
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Specification