Memory device capable of stable data writing
First Claim
1. A non-volatile memory device comprising:
- a plurality of memory cells;
a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells;
a first wire connected electrically to one end sides of said plurality of write select lines;
a second wire, connected electrically to a first voltage, and connected electrically to at least one of the other end sides of said plurality of write select lines in data writing;
a current supply circuit, in said data writing, activated to connect said first wire electrically to a second voltage and to thereby supply said data write current to said first wire; and
an address decode circuit receiving a third voltage different from said second voltage for selecting a write select line, whereinsaid second voltage is higher than said third voltage.
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Accused Products
Abstract
A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.
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Citations
3 Claims
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1. A non-volatile memory device comprising:
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a plurality of memory cells; a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells; a first wire connected electrically to one end sides of said plurality of write select lines; a second wire, connected electrically to a first voltage, and connected electrically to at least one of the other end sides of said plurality of write select lines in data writing; a current supply circuit, in said data writing, activated to connect said first wire electrically to a second voltage and to thereby supply said data write current to said first wire; and an address decode circuit receiving a third voltage different from said second voltage for selecting a write select line, wherein said second voltage is higher than said third voltage. - View Dependent Claims (2, 3)
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Specification
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- Resources
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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InventorsHidaka, Hideto
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Primary Examiner(s)Nguyen, Tuan T.
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Application NumberUS11/602,950Publication NumberTime in Patent Office349 DaysField of Search365/173, 365/230.03, 365/189.09US Class Current365/173CPC Class CodesG11C 11/15 using multiple magnetic lay...
