Data modem

• US 7,293,128 B2
• Filed: 12/14/2004
• Issued: 11/06/2007
• Est. Priority Date: 12/15/2000
• Status: Expired due to Fees

• Current Assignee: Elbit Systems of America LLC (Elbit Systems Limited)
• Original Assignee: Innovative Concepts, Inc. (Elbit Systems Limited)
• Inventors: Smith, Troy, Smith, Gregory N., Woodward, Robert A., Weinberger, Barry P., Wexler, Michael M., Feldstein, Andy A., Long, Shawn M.
• Primary Examiner(s): Myers; Paul R.
• Application Number:
  US11/010,478
• Publication Number:
  US 20070101040A1
• Time in Patent Office: 1,057 Days
• Field of Search: 710/306, 375/222
• US Class Current: 710/306
• CPC Class Codes: H04M 11/066 Telephone sets adapted for data transmision

Abstract

An improved data modem (IDM) and method includes a communication processor module, a mass storage module, a power converter module, and one or more DSP modules. The communication processor module utilizes commercial off-the-shelf components as well as electrically programmable logic devices (EPLD), which are programmed to provide a watchdog timer, programmable interrupt controller, flash page addressing, ISA bus decoder and controller, and various circuits and logic.

Claims

1. A data modem having an Input Output Module (IOM), wherein the IOM comprising:

a digital portion and an analog portion;

the digital portion comprises;

a digital signal processor (DSP);

a SDRAM bank connected to the DSP via an External Memory Interface (EMIF) bus;

a DSP-interface Field Programmable Logic Device (FPLD) interfaced to the DSP via the EMIF bus;

a watchdog implemented in a field programmable logic device;

a low-side driver interfaced to the DSP-interfaced FPLD, the DSP-interfaced FPLD including a multiplexer, controlled by a system reset, allowing signals to be routed to the low-side driver before the DSP-interface FPLD is loaded with operational code; and

Low Voltage Differential Signaling (LVDS) drivers/receivers.

2. The claim 1, wherein the analog portion comprises:

an Analog-Interface Field Programmable Logic Device (FPLD) connected to the LVDS drivers/receivers;

CODECS and analog circuitry connected to the analog-Interface FPLD;

ASK/FSK radio input/output circuits coupled to the CODECS and analog circuitry; and

radio control and status inputs/outputs coupled to the Analog-Interface FPLD.

3. The IOM of claim 1, wherein the watchdog comprises a counter and an associated software-accessible register, and wherein the watchdog is initialized by a software and operates under hardware control.

4. The IOM of claim 3, wherein the software-accessible register is accessed by periodically the software so as to reset the counter and to prevent the counter from reaching a terminal count during normal operation, and wherein the IOM is reset if the terminal count is reached.

5. The IOM of claim 1, wherein power is removed from the DSP and the SDRAM during a reset so as to force the SDRAM to reset and to allow the interface between the DSP and the SDRAM to operate properly.

6. The IOM of claim 1, wherein, using the multiplexer, the low-side driver is initialized before the DSP-interfaced FPLD is loaded with operational code.

7. The IOM of claim 2, further comprises a master clock connected to the CODECS, wherein a sampling phase of the CODECS is adjustable by increasing or decreasing the frequency of the master clock thereby effecting a shift in the sampling phase.