Logically partitioning different classes of TLB entries within a single caching structure

• US 7,293,157 B1
• Filed: 11/24/2004
• Issued: 11/06/2007
• Est. Priority Date: 11/24/2004
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jacobson, Quinn A., Parikh, Vipul Y.
• Primary Examiner(s): Sough; Hyung
• Assistant Examiner(s): RABOVIANSKI, ANTON I
• Application Number:
  US10/997,394
• Time in Patent Office: 1,077 Days
• Field of Search: 711/207, 711/147, 711/153, 711/206, 711/209, 711/216
• US Class Current: 711/207
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory

Abstract

One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside. If the corresponding location contains a TLB entry for the request, the system returns data from the TLB entry to facilitate the address translation. This hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure. In this way, the single caching structure can accommodate different classes of TLB entries at the same time.

Claims

1. A method for logically partitioning different classes of translation lookaside buffer (TLB) entries in a single caching structure, comprising:

receiving a request to lookup an address translation in the single caching structure;

applying a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside;

if the corresponding location contains a TLB entry for the request, returning data from the TLB entry to facilitate the address translation;

wherein the hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure, whereby the single caching structure can accommodate different classes of TLB entries at the same time;

wherein the different classes of TLB entries include;

a class of TLB entries for virtual-to-physical address translations, which translate a virtual address for a specific thread to a corresponding address in physical memory; and

a class of TLB entries for real-to-physical address translations, which translate a real address, associated with a specific processor in a multiprocessor system, to a corresponding address in physical memory; and

producing an address in physical memory in response to the request.

2. The method of claim 1,

wherein the hash function maps a TLB entry for a real-to-physical address translation to a lower-address portion of the single caching structure;

wherein the hash function first attempts to map a TLB entry for a virtual-to-physical address translation to the entire single caching structure, and if the first attempt collides with the lower-address portion of the single caching structure, the hash function remaps the TLB entry to a higher-address portion of the single caching structure.

3. The method of claim 1, wherein the hash function is applied to:

an address-to-be-translated; and

context information associated with the request.

4. The method of claim 3, wherein applying the hash function involves computing a hash index by performing exclusive-OR operations between bits of the address-to-be-translated and the context information.

5. The method of claim 1, wherein the hash function partitions the single caching structure so that operations associated with different classes of TLB entries do not interfere with each other.

6. The method of claim 1, wherein the hash function partitions the single caching structure so that different classes of TLB entries can be mapped to partitions of differing size.

7. The method of claim 1, wherein the single caching structure is associated with a memory management unit (MMU) within a computer system.

8. An apparatus that logically partitions different classes of translation lookaside buffer (TLB) entries in a single caching structure, comprising:

the single caching structure, which is configured to receive a request to lookup an address translation;

a lookup mechanism configured to apply a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside;

wherein if the corresponding location contains a TLB entry for the request, the lookup mechanism is configured to return data from the TLB entry to facilitate the address translation;

wherein the hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure, whereby the single caching structure can accommodate different classes of TLB entries at the same time;

wherein the different classes of TLB entries include;

a class of TLB entries for virtual-to-physical address translations, which translate a virtual address for a specific thread to a corresponding address in physical memory; and

a class of TLB entries for real-to-physical address translations, which translate a real address, associated with a specific processor in a multiprocessor system, to a corresponding address in physical memory; and

a producing mechanism configured to produce an address in physical memory in response to the request.

9. The apparatus of claim 8,

wherein the hash function maps a TLB entry for a real-to-physical address translation to a lower-address portion of the single caching structure;

wherein the hash function first attempts to map a TLB entry for a virtual-to-physical address translation to the entire single caching structure, and if the first attempt collides with the lower-address portion of the single caching structure, the hash function remaps the TLB entry to a higher-address portion of the single caching structure.

10. The apparatus of claim 8, wherein the hash function is applied to:

an address-to-be-translated; and

context information associated with the request.

11. The apparatus of claim 10, wherein while applying the hash function, the lookup mechanism is configured to compute a hash index by performing exclusive-OR operations between bits of the address-to-be-translated and the context information.

12. The apparatus of claim 8, wherein the hash function partitions the single caching structure so that operations associated with different classes of TLB entries do not interfere with each other.

13. The apparatus of claim 8, wherein the hash function partitions the single caching structure so that different classes of TLB entries can be mapped to partitions of differing size.

14. The apparatus of claim 8, wherein the single caching structure is associated with a memory management unit (MMU) within a computer system.

15. A computer system including a single caching structure that logically partitions different classes of translation lookaside buffer (TLB) entries, comprising:

at least one processor;

a physical memory;

the single caching structure, which is configured to receive a request to lookup an address translation;

a lookup mechanism configured to apply a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside;

wherein if the corresponding location contains a TLB entry for the request, the lookup mechanism is configured to return data from the TLB entry to facilitate the address translation;

wherein the hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure, whereby the single caching structure can accommodate different classes of TLB entries at the same time;

wherein the different classes of TLB entries include;

a class of TLB entries for virtual-to-physical address translations, which translate a virtual address for a specific thread to a corresponding address in physical memory; and

a class of TLB entries for real-to-physical address translations, which translate a real address, associated with a specific processor in a multiprocessor system, to a corresponding address in physical memory; and

a producing mechanism configured to produce an address in physical memory in response to the request.

16. The computer system of claim 15,

wherein the hash function maps a TLB entry for a real-to-physical address translation to a lower-address portion of the single caching structure;

wherein the hash function first attempts to map a TLB entry for a virtual-to-physical address translation to the entire single caching structure, and if the first attempt collides with the lower-address portion of the single caching structure, the hash function remaps the TLB entry to a higher-address portion of the single caching structure.

17. The computer system of claim 15, wherein the hash function is applied to:

an address-to-be-translated; and

context information associated with the request.

18. The computer system of claim 17, wherein while applying the hash function, the lookup mechanism is configured to compute a hash index by performing exclusive-OR operations between bits of the address-to-be-translated and the context information.

19. The computer system of claim 18, wherein the hash function partitions the single caching structure so that operations associated with different classes of TLB entries do not interfere with each other.

20. The computer system of claim 15, wherein the hash function partitions the single caching structure so that different classes of TLB entries can be mapped to partitions of differing size.

21. The computer system of claim 15, wherein the single caching structure is associated with a memory management unit (MMU) within a computer system.