Process for manufacturing an SOI wafer by annealing and oxidation of buried channels

• US 7,294,536 B2
• Filed: 12/20/2002
• Issued: 11/13/2007
• Est. Priority Date: 07/25/2000
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Villa, Flavio, Corona, Pietro, Barlocchi, Gabriele
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US10/327,702
• Publication Number:
  US 20030168711A1
• Time in Patent Office: 1,789 Days
• Field of Search: 438/39, 438/41, 438/42, 438/44, 438/196, 438/221, 438/222, 438/296, 438/311, 438/341, 438/359, 438/360, 438/424, 438/429, 438/442, 438/479, 438/404, 438/405, 438/410, 438/112, 438/149, 438/967, 438/422, 257/E21.561, 257/E21.562
• US Class Current: 438/149
• CPC Class Codes: H01L 21/3003 Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator

Abstract

A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Claims

1. A method, comprising:

forming in a first region of semiconductor material trenches separated by walls;

forming by epitaxial growth a second region of semiconductor material over the first region to form enclosed cavities from the trenches;

thermally annealing the first and second regions of semiconductor material; and

converting the walls into insulators after thermally annealing the first and second regions of semiconductor material.

2. The method of claim 1 wherein forming the second region of semiconductor material comprises forming the cavities such that the cavities hold a deoxidizing atmosphere.

3. The method of claim 1 wherein:

each of the cavities has a respective cross-sectional shape; and

thermally annealing the first and second regions of semiconductor material changes the cross-sectional shape of at least one of the cavities.

4. The method of claim 1, further comprising filling the cavities with an insulator after converting the walls to insulators.

5. The method of claim 1 wherein converting the walls into insulators comprises:

forming a trench opening around a surface region of the second region of semiconductor material; and

oxidizing the walls via the trench opening.

6. The method of claim 1, further comprising:

wherein converting the walls into insulators comprises,

forming a trench opening around a surface region of the second region of semiconductor material, and

oxidizing the walls via the trench opening; and

filling the cavities with an insulator after oxidizing the walls.

7. The method of claim 1 wherein thermally annealing the first and second regions of semiconductor material comprises heating the first and second regions at substantially 1150°

C. for substantially five hours.

8. The method of claim 1 wherein:

each of the walls has a respective cross-sectional shape; and

thermally annealing the first and second layers of semiconductor material changes the cross-sectional shape of at least one of the walls.

9. The method of claim 1 wherein forming the second region of semiconductor material comprises forming the second region from a semiconductor material that also composes the first region.

10. A process for manufacturing a SOI wafer, comprising:

forming in a semiconductor body buried cavities separated by walls;

thinning said walls by annealing said wafer in a deoxidizing atmosphere,

wherein when the annealing is complete said walls remain to separate the buried cavities;

opening a trench for providing access to said cavities from outside said wafer; and

providing oxygen to the buried cavities via the trench to completely oxidize said walls and form a buried insulating region.

11. The process of claim 10 wherein forming the buried cavities comprises:

forming trenches in a first region of the semiconductor body; and

forming a second region of the semiconductor body over the first region.

12. A process for manufacturing an SOI wafer, comprising the steps of:

forming, in a wafer of semiconductor material, buried cavities which delimit structures of said semiconductor material, wherein said step of forming buried cavities comprises entrapping hydrogen inside said cavities;

oxidizing completely said structures; and

performing, before said step of oxidizing, a step of thinning out said structures through a thermal process.

13. A process for manufacturing an SOI wafer, comprising the steps of:

forming, in a wafer of semiconductor material, buried cavities which delimit structures of said semiconductor material, wherein said step of forming cavities comprises the steps of;

opening first trenches in a substrate of said wafer; and

performing an epitaxial growth, so as to upwardly close said first trenches with said semiconductor material;

oxidizing completely said structures; and

performing, before said step of oxidizing, a step of thinning out said structures through a thermal process.

14. The process according to claim 13 wherein said structures comprise walls arranged side-by-side and separated from each other by said first trenches.

15. The process according to claim 14 wherein said first trenches are substantially rectilinear and have a height and a width smaller than said height, and in that the ratio between said height and said width is not smaller than 5.

16. The process according to claim 14 wherein said width is substantially equal to a width of said walls.

17. The process according to claim 14 wherein at the end of said step of thinning out, said cavities have a substantially circular cross-section.

18. The process according to claim 13 wherein said structures comprise columns.

19. A method, comprising:

forming in a first region of semiconductor material trenches separated by walls;

forming a second region of semiconductor material over the first region to form enclosed cavities from the trenches, wherein forming the second region of semiconductor material comprises forming the cavities such that the cavities hold a deoxidizing atmosphere;

thermally annealing the first and second regions of semiconductor material; and

converting the walls into insulators after thermally annealing the first and second regions of semiconductor material.

20. A process for manufacturing an SOI wafer, comprising the steps of:

forming, in a wafer of semiconductor material, cavities encapsulated by semiconductor material and which delimit structures of said semiconductor material;

oxidizing completely said structures;

performing, before beginning said step of oxidizing, a step of thinning out said structures through a thermal process;

wherein said step of thinning out comprises modifying the surface distribution of said semiconductor material around said cavities; and

wherein said step of modifying comprises annealing said wafer in a deoxidizing atmosphere.

21. A process for manufacturing an SOI wafer, comprising the steps of:

forming, in a wafer of semiconductor material, cavities encapsulated by semiconductor material and which delimit structures of said semiconductor material;

oxidizing completely said structures;

performing, before beginning said step of oxidizing, a step of thinning out said structures through a thermal process; and

wherein said step of forming buried cavities comprises entrapping hydrogen inside said cavities.

22. A process for manufacturing an SOI wafer, comprising the steps of:

forming, in a wafer of semiconductor material, cavities encapsulated by semiconductor material and which delimit structures of said semiconductor material;

oxidizing completely said structures;

performing, before beginning said step of oxidizing, a step of thinning out said structures through a thermal process; and

wherein said step of forming cavities comprises the steps of;

opening first trenches in a substrate of said wafer; and

performing an epitaxial growth, so as to upwardly close said first trenches with said semiconductor material.

23. The process according to claim 22, wherein said structures comprise walls arranged side-by-side and separated from each other by said first trenches.

24. The process according to claim 23 wherein said first trenches are substantially rectilinear and have a height and a width smaller than said height, and in that the ratio between said height and said width is not smaller than 5.

25. The process according to claim 23 wherein said width is substantially equal to a width of said walls.

26. The process according to claim 23 wherein at the end of said step of thinning out, said cavities have a substantially circular cross-section.

27. The process according to claim 22, wherein said structures comprise columns.