Method for fabricating silicon nitride spacer structures

• US 7,294,581 B2
• Filed: 10/17/2005
• Issued: 11/13/2007
• Est. Priority Date: 10/17/2005
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Iyer, R. Suryanarayanan, Tandon, Sanjeev
• Primary Examiner(s): Sarkar; Asok K.
• Assistant Examiner(s): Yevsikov; Victor V.
• Application Number:
  US11/253,229
• Publication Number:
  US 20070087575A1
• Time in Patent Office: 757 Days
• Field of Search: 438/758, 438/396, 438/761, 438/458
• US Class Current: 438/761
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over which the spacer structure is to be formed. The spacer structure may be formed over the base structure by depositing a first layer comprising silicon nitride on the base structure, depositing a second layer comprising a silicon-based dielectric material on the first layer, and depositing a third layer comprising silicon nitride on the second layer. The first, second, and third layers are deposited in a single processing reactor.

Claims

1. A method for fabricating a spacer structure on a semiconductor substrate, comprising:

providing a substrate containing a base structure over which the spacer structure is to be formed; and

forming the spacer structure by;

(a) depositing a first layer comprising silicon nitride on the base structure;

(b) depositing a second layer comprising a silicon-based dielectric material on the first layer; and

(c) depositing a third layer comprising silicon nitride on the second layer;

wherein steps (a)-(c) are performed in a single processing reactor, and wherein step (b) further comprises maintaining a vacuum while depositing the second layer.

2. The method of claim 1, wherein the first layer is about 20-1500 Angstroms thick.

3. The method of claim 1, wherein the first layer further comprises:

at least one dopant comprising boron, carbon, germanium, or hydrogen.

4. The method of claim 1, wherein the silicon-based dielectric material of the second layer comprises silicon oxide or silicon oxynitride.

5. The method of claim 4, wherein the second layer is about 20-1500 Angstroms thick.

6. The method of claim 4, wherein the base structure is a gate structure of a transistor.

7. The method of claim 6, wherein step (a) further comprises depositing the first layer on sidewalls of the gate structure and regions of the substrate proximate the gate structure.

8. The method of claim 6, wherein the gate structure comprises a gate dielectric layer and a gate layer.

9. The method of claim 8, wherein the gate dielectric layer comprises at least one film formed from silicon oxide, silicon oxynitride, hafnium oxide, or hafnium silicate.

10. The method of claim 8, wherein the gate layer is formed from polysilicon.

11. The method of claim 1, wherein the silicon-based dielectric material of the second layer is formed from silicon nitride doped with at least one of boron, carbon, or oxygen.

12. The method of claim 11, wherein the second layer is about 20-1500 Angstroms thick.

13. The method of claim 11, wherein the second layer is about 500 Angstroms thick.

14. The method of claim 11, wherein the base structure comprises an exposed metallic layer.

15. The method of claim 1, wherein the third layer is about 20-1500 Angstroms thick.

16. The method of claim 1, wherein the spacer structure has a total thickness of about 100-1500 Angstroms.

17. The method of claim 1, wherein the spacer structure has a total thickness of about 600 Angstroms.

18. The method of claim 1, wherein the thickness of at least one of the first through third layers is varied in response to the diffusivity of elements contained in the second layer at a given thermal budget.

19. The method of claim 1, wherein step (b) further comprises depositing the second layer via at least one of a chemical vapor deposition process or an atomic layer deposition process.

20. The method of claim 1, wherein steps (a) through (c) are performed under continuous vacuum conditions.

21. A method for fabricating a spacer structure on a semiconductor substrate, comprising:

providing a substrate containing a base structure over which the spacer structure is to be formed; and

forming the spacer structure by;

(a) depositing a first layer comprising silicon nitride on the base structure;

(b) depositing a second layer comprising a silicon-based dielectric material on the first layer; and

(c) depositing a third layer comprising silicon nitride on the second layer;

wherein steps (a)-(c) are performed in a single processing reactor under continuous vacuum conditions.