Low temperature silicon compound deposition
First Claim
1. A method of fabricating integrated circuits, comprising:
- depositing by chemical vapor deposition a silicon layer of a thickness of more than one monolayer on a plurality of substrates in a hot wall batch process chamber by exposing the substrates to a supply of trisilane;
interrupting the supply of trisilane;
forming a silicon compound layer by exposing the silicon layer to a reactive species after interrupting the supply, wherein the silicon compound layer has a thickness non-uniformity of about 5% or less and a step coverage of about 80% or greater; and
further comprising repeating depositing, interrupted and forming in a plurality of cycles.
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Accused Products
Abstract
Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride layer is then formed by nitriding the silicon layer with nitrogen radicals, such as by pulsing the plasma power (remote or in situ) on after a trisilane step. The nitrogen radical supply is stopped. Optionally non-activated ammonia is also supplied, continuously or intermittently. If desired, the process is repeated for greater thickness, purging the reactor after each trisilane and silicon compounding step to avoid gas phase reactions, with each cycle producing about 5-7 angstroms of silicon nitride.
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Citations
44 Claims
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1. A method of fabricating integrated circuits, comprising:
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depositing by chemical vapor deposition a silicon layer of a thickness of more than one monolayer on a plurality of substrates in a hot wall batch process chamber by exposing the substrates to a supply of trisilane; interrupting the supply of trisilane; forming a silicon compound layer by exposing the silicon layer to a reactive species after interrupting the supply, wherein the silicon compound layer has a thickness non-uniformity of about 5% or less and a step coverage of about 80% or greater; and further comprising repeating depositing, interrupted and forming in a plurality of cycles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of semiconductor processing, comprising:
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establishing reaction rate limited chemical vapor deposition conditions in a hot wall batch reactor chamber; depositing a silicon layer on each of a plurality of substrates in the chamber by exposing the substrates to a silicon source, wherein the silicon layer has a thickness between about 3 Å and
about 30 Å
, wherein the silicon source is trisilane;interrupting flow of the silicon source and removing the silicon source from the batch reactor chamber; and exposing the silicon layer to radicals to form a silicon compound layer having a thickness non-uniformity of about 5% or less and a step coverage of about 80% or greater, wherein depositing the silicon layer is performed a plurality of times to deposit a plurality of silicon layers over each of the substrates, wherein trisilane is the silicon source used to deposit a first of the silicon layers. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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Specification