Low temperature silicon compound deposition

• US 7,294,582 B2
• Filed: 08/25/2005
• Issued: 11/13/2007
• Est. Priority Date: 07/19/2002
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Pomarede, Christophe F., Todd, Michael A., De Blank, Marinus J., van der Jeugd, Cornelius A., Wan, Yuet Mei, Beulens, Jacobus Johannes, Weeks, Keith D., Werkhoven, Christian J., Haverkort, Ruben
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US11/213,449
• Publication Number:
  US 20060088985A1
• Time in Patent Office: 810 Days
• Field of Search: 438/763, 438/775, 438/786, 438/791, 438/726, 257/E21.192, 257/E21.267, 257/E21.268
• US Class Current: 438/763
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/4408 by purging residual gases from the reaction chamber or gas lines
• CPC Class Codes: C23C 16/45523 Pulsed gas flow or change of composition over time
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02329 introduction of nitrogen
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3185 of siliconnitrides

Abstract

Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride layer is then formed by nitriding the silicon layer with nitrogen radicals, such as by pulsing the plasma power (remote or in situ) on after a trisilane step. The nitrogen radical supply is stopped. Optionally non-activated ammonia is also supplied, continuously or intermittently. If desired, the process is repeated for greater thickness, purging the reactor after each trisilane and silicon compounding step to avoid gas phase reactions, with each cycle producing about 5-7 angstroms of silicon nitride.

Claims

1. A method of fabricating integrated circuits, comprising:

depositing by chemical vapor deposition a silicon layer of a thickness of more than one monolayer on a plurality of substrates in a hot wall batch process chamber by exposing the substrates to a supply of trisilane;

interrupting the supply of trisilane;

forming a silicon compound layer by exposing the silicon layer to a reactive species after interrupting the supply, wherein the silicon compound layer has a thickness non-uniformity of about 5% or less and a step coverage of about 80% or greater; and

further comprising repeating depositing, interrupted and forming in a plurality of cycles.

2. The method of claim 1, wherein depositing the silicon layer comprises maintaining process conditions selected to achieve reaction rate limited deposition.

3. The method of claim 2, wherein depositing the silicon layer is performed at a temperature of about 600°

C. or less.

4. The method of claim 3, wherein the temperature is about 500°

C. or less.

5. The method of claim 4, wherein the temperature is about 400-450°

C.

6. The method of claim 2, wherein exposing the substrates to the supply of trisilane comprises establishing a trisilane partial pressure of about 10 mTorr or less.

7. The method of claim 6, wherein the trisilane partial pressure is about 3-4 mTorr.

8. The method of claim 2, wherein exposing the substrates to the supply of trisilane comprises exposing the substrates to trisilane for about 30-120 seconds.

9. The method of claim 1, wherein forming the silicon compound layer comprises exposing the silicon layer to plasma-activated reactive species.

10. The method of claim 9, wherein forming the silicon compound layer comprises activating the reactive species in a remote microwave radical generator.

11. The method of claim 9, wherein forming the silicon compound layer comprises activating the reactive species within the batch process chamber.

12. The method of claim 11, wherein activating the reactive species within the batch process chamber comprises supplying current to a conductor coil within the batch process chamber.

13. The method of claim 12, wherein the conductor coil is housed within an evacuated insulating sleeve and reactive species are formed outside the insulating sleeve and within the batch process chamber.

14. The method of claim 9, wherein the plasma-activated reactive species comprises nitrogen radicals.

15. The method of claim 9, further comprising supplying ammonia into the process chamber.

16. The method of claim 15, wherein supplying ammonia comprises first intermixing the ammonia with the plasma-activated reactive species in the process chamber.

17. The method of claim 16, wherein intermixing the ammonia with the plasma-activated reactive species activates the ammonia to form nitrogen radicals from the ammonia.

18. The method of claim 1, wherein depositing the silicon layer comprises forming the silicon layer to a thickness equal to or greater than the nitridation saturation depth.

19. The method of claim 1, wherein the reactive species comprises a nitrogen species and the silicon-containing compound layer comprises silicon nitride.

20. The method of claim 19, wherein the silicon nitride layer is more uniform than a silicon nitride layer of substantially similar thickness deposited by chemical vapor deposition with silane.

21. A method of semiconductor processing, comprising:

establishing reaction rate limited chemical vapor deposition conditions in a hot wall batch reactor chamber;

depositing a silicon layer on each of a plurality of substrates in the chamber by exposing the substrates to a silicon source, wherein the silicon layer has a thickness between about 3 Å and

about 30 Å

, wherein the silicon source is trisilane;

interrupting flow of the silicon source and removing the silicon source from the batch reactor chamber; and

exposing the silicon layer to radicals to form a silicon compound layer having a thickness non-uniformity of about 5% or less and a step coverage of about 80% or greater,

wherein depositing the silicon layer is performed a plurality of times to deposit a plurality of silicon layers over each of the substrates, wherein trisilane is the silicon source used to deposit a first of the silicon layers.

22. The method of claim 21, wherein the radicals comprise nitrogen and the silicon compound is silicon nitride.

23. The method of claim 21, wherein exposing the silicon layer to radicals comprises exposing the silicon layer to ammonia and plasma-activated radicals.

24. The method of claim 23, wherein the plasma-activated radicals are nitrogen radicals.

25. The method of claim 23, wherein the plasma-activated radicals are one or more species chose from the group consisting of argon, hydrogen and helium radicals.

26. The method of claim 23, wherein exposing the silicon layer to radicals comprises generating the plasma-activated radicals in situ.

27. The method of claim 21, wherein exposing the silicon layer to radicals comprises remotely generating the plasma-activated radicals and supplying the plasma activated-radicals to the reactor chamber.

28. The method of claim 21, wherein exposing the silicon layer to radicals comprises exposing the silicon layer to plasma-activated nitrogen radicals and to one or more species chose from the group consisting of argon, hydrogen and helium radicals.

29. The method of claim 21, wherein depositing, interrupting and exposing comprises continuously flowing N₂ into the batch reactor chamber, wherein exposing comprises providing power to a radical generator to generate radicals.

30. The method of claim 29, wherein depositing, interrupting and exposing comprises continuously flowing NH₃ into the batch reactor chamber.

31. The method of claim 22, wherein the layer of an insulating silicon compound has a stoichiometry of about 45 silicon atoms per 56 nitrogen atoms.

32. The method of claim 21, wherein the radicals comprise oxygen and wherein the silicon compound is silicon oxide.

33. The method of claim 21, wherein the silicon source for depositing subsequent silicon layers after depositing the first silicon layer comprises one or more silicon precursors selected from the group consisting of silanes having a silane chemical formula Si_nH_2n+2, where n=1 to 4, and halosilanes having a halosilane chemical formula R_4-XSiH_X, where R=Cl, Br or I and X=0 to 3.

34. The method of claim 33, wherein a first substrate temperature for depositing the first silicon layer is less than about 500°

C.

35. The method of claim 21, wherein depositing, interrupting and exposing are performed at a temperature of less than about 600°

C.

36. The method of claim 21, wherein depositing the silicon layer comprises providing trisilane through a gas injector.

37. The method of claim 36, wherein the gas injector has a plurality of openings along a height of the batch reactor chamber.

38. The method of claim 21, wherein removing the silicon source comprises purging the process chamber with inert gas.

39. The method of claim 21, wherein removing the silicon source comprises performing one or more removal processes selected from the group consisting of evacuation of the silicon source, or displacement of the silicon source gas by a gas carrying radicals.

40. The method of claim 21, further comprising removing the radicals and exposing the substrates an other reactive species.

41. The method of claim 40, wherein the other reactive species is a dopant.

42. The method of claim 21, wherein exposing the silicon layer to radicals forms a gate dielectric layer.

43. The method of claim 42, further comprising forming a gate electrode over the gate dielectric layer.

44. The method of claim 21, wherein the reaction chamber is configured to accommodate a wafer boat, the wafer boat configured to accommodate the plurality of substrates.