Top layers of metal for high performance IC's

• US 7,294,870 B2
• Filed: 05/04/2005
• Issued: 11/13/2007
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Soward; Ida M.
• Application Number:
  US11/121,477
• Publication Number:
  US 20050200023A1
• Time in Patent Office: 923 Days
• Field of Search: 257207-209, 257/211, 257758-760, 257/700
• US Class Current: 257/211
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate;

an interconnecting metallization structure over said silicon substrate, said interconnecting metallization structure comprising multiple lower metal layers;

a dielectric layer between said multiple lower metal layers;

a passivation layer over said interconnecting metallization structure and over said dielectric layer, wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip and a topmost nitride layer of said semiconductor chip, wherein said topmost nitride layer is over said topmost oxide layer;

a polymer layer over said passivation layer, said polymer layer having a thickness greater than that of said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers and greater than that of said dielectric layer, and wherein said interconnecting metallization structure comprises multiple contact points exposed by multiple first openings in said passivation layer and by multiple second openings in said polymer layer, wherein said multiple first openings are aligned with said multiple second openings, wherein said multiple contact points are separate from one another; and

an upper metallization structure over said polymer layer and over said multiple contact points, wherein a connecting portion of said upper metallization structure connects at least one portion of said interconnecting metallization structure with at least one other portion of said interconnecting metallization structure through said multiple first and second openings, and wherein said connecting portion comprises electroplated copper and has a thickness greater than those of said multiple lower metal layers.

2. The semiconductor chip of claim 1, wherein said semiconductor devices and said interconnecting metallization structure comprise a sub-micron integrated circuit.

3. The semiconductor chip of claim 1, wherein said interconnecting metallization structure comprises a sub-micron metal.

4. The semiconductor chip of claim 1, wherein said upper metallization structure comprises a tens-micron interconnecting metallization.

5. The semiconductor chip of claim 1, wherein said topmost nitride layer comprises silicon nitride.

6. The semiconductor chip of claim 1, wherein said topmost nitride layer has a thickness between about 0.5 micrometers and 2 micrometers.

7. The semiconductor chip of claim 1, wherein said topmost oxide layer comprises CVD oxide.

8. The semiconductor chip of claim 1, wherein said topmost oxide layer has a thickness between about 0.15 micrometers and 2 micrometers.

9. The semiconductor chip of claim 1, wherein said upper metallization structure comprises nickel.

10. The semiconductor chip of claim 1, wherein said upper metallization structure comprises electroless metal.

11. The semiconductor chip of claim 1, wherein said upper metallization structure comprises aluminum.

12. The semiconductor chip of claim 1, wherein said upper metallization structure comprises chromium.

13. The semiconductor chip of claim 1, wherein said upper metallization structure comprises tungsten.

14. The semiconductor chip of claim 1, wherein said upper metallization structure comprises one or more upper metal layers, and at least one of said one or more upper metal layers has a thickness greater than that of each of said multiple lower metal layers.

15. The semiconductor chip of claim 1 further comprising another polymer layer between two neighboring layers of multiple upper metal layers of said upper metallization structure.

16. The semiconductor chip of claim 1 further comprising another polymer layer over a topmost one of one or more upper metal layers of said upper metallization structure.

17. The semiconductor chip of claim 1, wherein said polymer layer comprises a photosensitive polymer.

18. The semiconductor chip of claim 1, wherein said polymer layer comprises a non-photosensitive polymer.

19. The semiconductor chip of claim 1, wherein said polymer layer comprises polymide.

20. The semiconductor chip of claim 1, wherein said polymer layer comprises benzocyclobutene (BCB).

21. The semiconductor chip of claim 1, wherein the diameter of at least one of said multiple first openings is between about 0.5 micrometers and 3 micrometers.

22. The semiconductor chip of claim 1, wherein said multiple contact points comprise tungsten.

23. The semiconductor chip of claim 1, wherein said multiple contact points comprise electroplated metal.

24. The semiconductor chip of claim 1, wherein said multiple contact points comprise electroless metal.

25. The semiconductor chip of claim 1, wherein said connecting portion is connected to said multiple contact points through said multiple first and second openings.

26. The semiconductor chip of claim 25, wherein the size of at least one of said multiple contact points exposed by said multiple first and second openings is between about 0.3 micrometers and 5 micrometers.

27. The semiconductor chip of claim 25, wherein said multiple contact points comprise copper.

28. The semiconductor chip of claim 25, wherein said multiple contact points comprise aluminum.

29. The semiconductor chip of claim 1 further comprising a bump connected to said upper metallization structure.

30. The semiconductor chip of claim 1 further comprising a solder bump connected to said upper metallization structure.

31. The semiconductor chip of claim 1 further comprising a wirebonding interconnect pad.

32. The semiconductor chip of claim 1, wherein said interconnecting metallization structure comprises copper, aluminum, or tungsten.

33. The semiconductor chip of claim 1, wherein said multiple semiconductor devices are connected to said interconnecting metallization structure.

34. The semiconductor chip of claim 1, wherein said semiconductor devices comprise transistors.

35. The semiconductor chip of claim 1 wherein said semiconductor devices comprise polysilicon.

36. The semiconductor chip of claim 1 wherein said connecting portion connects at least one of said semiconductor devices with at least another one of said semiconductor devices through said interconnecting metallization structure.

37. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a signal distribution interconnect.

38. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a power distribution interconnect.

39. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a ground distribution interconnect.

40. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a clock distribution network.

41. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a signal line or a signal plane.

42. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a power line or a power plane.

43. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a ground line or a ground plane.

44. The semiconductor chip of claim 1, wherein said upper metallization structure comprises an upper metal layer, and said polymer layer is under said upper metal layer.

45. The semiconductor chip of claim 1, wherein said upper metallization structure comprises one or more upper metal layers, and said polymer layer is under a bottommost one of said one or more upper metal layers and is over said passivation layer.

46. The semiconductor chip of claim 1 further comprising another polymer layer over an upper metal layer of said upper metallization structure.

47. A semiconductor wafer comprising:

one or more semiconductor chips comprising;

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate;

an interconnecting metallization structure over said silicon substrate, said interconnecting metallization structure comprising multiple lower metal layers;

a dielectric layer between said multiple lower metal layers;

a passivation layer over said interconnecting metallization structure and over said dielectric layer, wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip and a topmost nitride layer of said semiconductor chip, wherein said topmost nitride layer is over said topmost oxide layer;

a polymer layer over said passivation layer, said polymer layer having a thickness greater than that of said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers and greater than that of said dielectric layer, and wherein said interconnecting metallization structure comprises multiple contact points exposed by multiple first openings in said passivation layer and by multiple second openings in said polymer layer, wherein said multiple first openings are aligned with said multiple second openings; and

an upper metallization structure over said polymer layer, wherein a connecting portion of said upper metallization structure connects at least one portion of said interconnecting metallization structure with at least one other portion of said interconnecting metallization structure through said multiple first and second openings, and wherein said connecting portion comprises an electroplated metal and has a thickness greater than those of said multiple lower metal layers.

48. The semiconductor wafer of claim 47, wherein said semiconductor devices and said interconnecting metallization structure comprise a sub-micron integrated circuit.

49. The semiconductor wafer of claim 47, wherein said interconnecting metallization structure comprises a sub-micron metal.

50. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises a tens-micron interconnecting metallization.

51. The semiconductor wafer of claim 47, wherein said topmost nitride layer comprises silicon nitride.

52. The semiconductor wafer of claim 47, wherein said topmost nitride layer has a thickness between about 0.5 micrometers and 2 micrometers.

53. The semiconductor wafer of claim 47, wherein said topmost oxide layer comprises CVD oxide.

54. The semiconductor wafer of claim 47, wherein said topmost oxide layer has a thickness between about 0.15 micrometers and 2 micrometers.

55. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises nickel.

56. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises electroless metal.

57. The semiconductor wafer of claim 47, wherein said electroplated metal comprises copper.

58. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises aluminum.

59. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises chromium.

60. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises tungsten.

61. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises one or more upper metal layers, and at least one of said one or more upper metal layers has a thickness greater than that of each of said multiple lower metal layers.

62. The semiconductor wafer of claim 47 further comprising another polymer layer between two neighboring layers of multiple upper metal layers of said upper metallization structure.

63. The semiconductor wafer of claim 47 further comprising another polymer layer over a topmost one of one or more upper metal layers of said upper metallization structure.

64. The semiconductor wafer of claim 47, wherein said polymer layer comprises a photosensitive polymer.

65. The semiconductor wafer of claim 47, wherein said polymer layer comprises a non-photosensitive polymer.

66. The semiconductor wafer of claim 47, wherein said polymer layer comprises polyimide.

67. The semiconductor wafer of claim 47, wherein said polymer layer comprises benzocyclobutene (BCB).

68. The semiconductor wafer of claim 47, wherein the diameter of at least one of said multiple first openings is between about 0.5 micrometers and 3 micrometers.

69. The semiconductor wafer of claim 47, wherein said multiple contact points comprise tungsten.

70. The semiconductor wafer of claim 47, wherein said multiple contact points comprise electroplated metal.

71. The semiconductor wafer of claim 47, wherein said multiple contact points comprise electroless metal.

72. The semiconductor wafer of claim 47, wherein said connecting portion is connected to said multiple contact points through said multiple first and second openings.

73. The semiconductor wafer of claim 72, wherein the size of at least one of said multiple contact points exposed by said multiple first and second openings is between about 0.3 micrometers and 5 micrometers.

74. The semiconductor wafer of claim 72, wherein said multiple contact points comprise copper.

75. The semiconductor wafer of claim 72, wherein said multiple contact points comprise aluminum.

76. The semiconductor wafer of claim 47 further comprising a bump connected to said upper metallization structure.

77. The semiconductor wafer of claim 47 further comprising a solder bump connected to said upper metallization structure.

78. The semiconductor wafer of claim 47 further comprising a wirebonding interconnect pad.

79. The semiconductor wafer of claim 47, wherein said interconnecting metallization structure comprises copper, aluminum, or tungsten.

80. The semiconductor wafer of claim 47, wherein said multiple semiconductor devices are connected to said interconnecting metallization structure.

81. The semiconductor wafer of claim 47, wherein said semiconductor devices comprise transistors.

82. The semiconductor wafer of claim 47, wherein said semiconductor devices comprise polysilicon.

83. The semiconductor wafer of claim 47, wherein said connecting portion connects at least one of said semiconductor devices with at least another one of said semiconductor devices through said interconnecting metallization structure.

84. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a signal distribution interconnect.

85. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a power distribution interconnect.

86. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a ground distribution interconnect.

87. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a clock distribution network.

88. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a signal line or a signal plane.

89. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a power line or a power plane.

90. The semiconductor wafer of claim 47, wherein said connecting portion of said upper metallization structure comprises a ground line or a ground plane.

91. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises an upper metal layer, and said polymer layer is under said upper metal layer.

92. The semiconductor wafer of claim 47, wherein said upper metallization structure comprises one or more upper metal layers, and said polymer layer is under a bottommost one of said one or more upper metal layers and is over said passivation layer.

93. The semiconductor wafer of claim 47 further comprising another polymer layer over an upper metal layer of said upper metallization structure.