Nanotube-on-gate FET structures and applications

• US 7,294,877 B2
• Filed: 03/26/2004
• Issued: 11/13/2007
• Est. Priority Date: 03/28/2003
• Status: Expired due to Fees

• Current Assignee: Nantero Incorporated, Texas Instruments, Inc.
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Brock, Darren K., Segal, Brent M., Rueckes, Thomas, Jaiprakash, Venkatachalam C., Vogeli, Bernard
• Primary Examiner(s): Purvis; Sue A.
• Assistant Examiner(s): Rodela; Eduardo A.
• Application Number:
  US10/811,373
• Publication Number:
  US 20050056877A1
• Time in Patent Office: 1,327 Days
• Field of Search: 257/E23.074, 257/E23.165, 257/E51.04
• US Class Current: 257/296
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2213/17 Memory cell being a nanowire transistor
• CPC Class Codes: G11C 23/00 Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10K 10/481 characterised by the gate conductors
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene

Abstract

Nanotube on gate FET structures and applications of such, including n² crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region. Certain embodiments of the device have an area of about 4 F². Other embodiments include a release line is positioned in spaced relation to the nanotube switching element, and having a horizontal orientation that is parallel to the orientation of the source and drain diffusions. Other embodiments provide an n² crossbar array having n² non-volatile transistor devices, but require only 2n control lines.

Claims

1. A non-volatile transistor device, comprising

a source region and a drain region of a first semiconductor type of material;

a channel region of a second semiconductor type of material disposed between the source and drain region;

a gate structure made of at least one of semiconductive or conductive material and disposed over an insulator over the channel region;

a control structure including an electromechanically-deflectable nanotube switching element in spaced relation to the gate structure and capable of a deflected state and an undeflected state,

wherein the device has a network of inherent capacitances, including an inherent capacitance between the gate structure and the nanotube switching element when the nanotube switching element is in the undeflected state, such that electrical stimulus at the control structure and at least one of the source and drain regions deflects the nanotube switching element into the deflected state and thus into contact with the gate structure.

2. The non-volatile transistor device of claim 1 wherein the nanotube switching element comprises an article formed from a porous fabric of nanotubes.

3. The non-volatile transistor device of claim 2 wherein the fabric comprises substantially a monolayer of nanotubes.

4. The non-volatile transistor device of claim 1 wherein the nanotubes comprise single-walled carbon nanotubes.

5. The non-volatile transistor device of claim 1 wherein the source and drain regions are disposed on or in a horizontal substrate and wherein the nanotube switching element is suspended horizontally in relation to the horizontal substrate.

6. The non-volatile transistor device of claim 5 wherein the source and drain regions are formed as diffusions and one of the source and drain diffusions is a selection line for the device, and wherein the nanotube switching element is a second selection line for the device.

7. The non-volatile transistor device of claim 6 wherein the source and drain regions are disposed orthogonal to the nanotube element.

8. The non-volatile transistor device of claim 7 wherein the device has an area of about 4 F₂.

9. The non-volatile transistor device of claim 7 further comprising a release line positioned in spaced relation to the nanotube switching element, and having a horizontal orientation that is parallel to the orientation of the source and drain diffusions.

10. The non-volatile transistor device of claim 9 wherein the device includes a metallic layer disposed on the release line on a surface facing the nanotube switching element.

11. The non-volatile transistor device of claim 5 wherein the nanotube switching element is supported by supports having a known dielectric characteristic and wherein the geometry of the supports is of a tailored size to create a known inherent capacitance between the gate structure and the nanotube switching element when the nanotube switching element is in the undeflected state, and wherein said known inherent capacitance has a known ratio relationship to an inherent capacitance between the gate structure and the channel region.

12. The non-volatile transistor device of claim 11 wherein the ratio relationship is about 0.25.

13. The non-volatile transistor device of claim 1 wherein the device includes a metallic layer disposed on the gate structure on a surface facing the nanotube switching element.

14. The non-volatile transistor device of claim 1 wherein device has an area of about 4 F² and is a bit-selectable read/write device.

15. The non-volatile transistor device of claim 1 wherein the contact between the nanotube switching element and the gate structure is a non-volatile state.

16. The non-volatile transistor device of claim 1, wherein a first portion of the nanotube switching element is suspended over the gate structure and wherein a second portion of the nanotube switching element is disposed on a surface.

17. The non-volatile transistor device of claim 16, wherein the control structure further comprises an electrode, and wherein the first portion of the nanotube switching element provides a conductive pathway from the electrode to the second portion of the nanotube switching element.

18. The non-volatile transistor of claim 17, wherein the electrode comprises one of a conductive material and a semiconductive material.

19. A method of operating an array of transistor devices in which each transistor device has a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region, and wherein each transistor device further includes a gate structure made of at least one of semiconductive or conductive material and disposed over an insulator over the channel region, a control structure including an electromechanically-deflectable nanotube switching element in spaced relation to the gate structure, and wherein each transistor device further includes a release line positioned in spaced relation to the nanotube switching element, the method comprising the acts of:

applying substantially the same voltage values to the source and drain diffusions;

applying a voltage to the nanotube switching element sufficient to deflect it into contact with the gate structure;

applying voltages to the release line and the nanotube switching element for the devices to be written with voltages to place the nanotube switching element in a corresponding information state.

20. The method of claim 19 further comprising the act of applying a different set of voltages to the release line and the nanotube switching elements for the other devices in the array, not to be written to.

21. The method of claim 20 wherein the different set of voltages are sufficiently low to prevent write disturbs to adjacent devices in the array.

22. A crossbar array having n input lines and n output lines, comprising:

n² non-volatile transistor devices, each device including

a source region and a drain region of a first semiconductor type of material;

a channel region of a second semiconductor type of material disposed between the source and drain region;

a gate structure made of at least one of semiconductive or conductive material and disposed over an insulator over the channel region;

a control structure including an electromechanically-deflectable nanotube switching element in spaced relation to the gate structure;

the nanotube switching element being deflectable into non-volatile contact with the gate structure in response to signals being applied to the control structure and one of the source region and drain region; and

a release line positioned in spaced relation to the nanotube switching element;

a switch line decoder providing n select lines, each select line coupled to one of the source and drain regions of each device of a corresponding set of devices; and

a release line decoder providing n select lines, each release line coupled to a release line of each device of a corresponding set of devices.