Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
First Claim
1. A multi-layer semiconductor wafer structure defining a multiplicity of dies formed thereon, said wafer structure comprising:
- at least two first scribe lines having a selected width S1, each of said at least two first scribe lines extending along a first orientation and defining a first edge of at least two first dies of said multiplicity of dies;
at least two second scribe lines having a selected width S2, each of said at least two second scribe lines extending along a second orientation and defining a second edge of at least two second dies and intersecting said at least two first scribe lines, and said first edges of said at least two first dies and said second edges of said at least two second dies intersecting at corner points;
first restricted areas A1 defined on said first scribe line where placement of a test key is restricted, and said first restricted areas A1 being defined by the equation A1=D1×
S1, where D1 is the distance along the first edge extending from a corner point of said at least two first dies;
second restricted areas AS at intersections of said at least two first scribe lines and said at least two second scribe lines, said second restricted areas AS being defined by the equation AS=S1×
S2;
at least one first test key formed on each one of said at least two first and said at least two second scribe lines, but not on said restricted areas A and AS; and
at least one second test key formed in at least one of said A1 restricted areas and said AS restricted areas.
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Abstract
A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
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Citations
30 Claims
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1. A multi-layer semiconductor wafer structure defining a multiplicity of dies formed thereon, said wafer structure comprising:
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at least two first scribe lines having a selected width S1, each of said at least two first scribe lines extending along a first orientation and defining a first edge of at least two first dies of said multiplicity of dies; at least two second scribe lines having a selected width S2, each of said at least two second scribe lines extending along a second orientation and defining a second edge of at least two second dies and intersecting said at least two first scribe lines, and said first edges of said at least two first dies and said second edges of said at least two second dies intersecting at corner points; first restricted areas A1 defined on said first scribe line where placement of a test key is restricted, and said first restricted areas A1 being defined by the equation A1=D1×
S1, where D1 is the distance along the first edge extending from a corner point of said at least two first dies;second restricted areas AS at intersections of said at least two first scribe lines and said at least two second scribe lines, said second restricted areas AS being defined by the equation AS=S1×
S2;at least one first test key formed on each one of said at least two first and said at least two second scribe lines, but not on said restricted areas A and AS; and at least one second test key formed in at least one of said A1 restricted areas and said AS restricted areas. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification