Process and circuit for protection of test contacts in high current measurement of semiconductor components

• US 7,295,021 B2
• Filed: 03/15/2005
• Issued: 11/13/2007
• Est. Priority Date: 03/15/2004
• Status: Active Grant

• Current Assignee: T.I.P.S. Messtechnik GmbH
• Original Assignee: T.I.P.S. Messtechnik GmbH
• Inventors: Gaggl, Rainer
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US11/079,303
• Publication Number:
  US 20060091898A1
• Time in Patent Office: 973 Days
• Field of Search: None
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/06766 Input circuits therefor
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments

Abstract

To limit the current in heavy current testing of semiconductor components with test needles, upstream of each needle a circuit is connected which has low resistance in the range of allowable currents and has high resistance above a given limit current in order to limit the current. The current source which undertakes limitation in the electrical supply lead to the probes is galvanically separated from the voltage supply of the current source itself.

Claims

1. A process for limiting a test current in heavy current testing of semiconductor components with test needles, comprising the steps of:

connecting upstream of each needle a circuit that is connected to a voltage supply, the circuit having at least one circuit component which has low resistance in the range of allowable test currents and has high resistance above a given limit current in order to limit the test current; and

supplying a control voltage or current to the at least one circuit component, wherein the supply of the control voltage or current is carried out galvanically separated from the voltage supply of the circuit.

2. The process as claimed in claim 1, wherein the at least one circuit component is a MOS-FET transistor or bipolar transistor.

3. The process as claimed in claim 1, wherein the control voltage is supplied from DC-DC converter or a battery.

4. The process as claimed in claim 2, wherein the at least one circuit component is the MOS-FET transistor and wherein the test current is limited due to saturation of a drain current of the MOS-FET transistor.

5. The process as claimed in claim 2, wherein the at least one circuit component is the bipolar transistor and wherein the test current is limited due to saturation of a collector current of the bipolar transistor.