Programmable logic device with enhanced logic block architecture

• US 7,295,035 B1
• Filed: 08/09/2005
• Issued: 11/13/2007
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Cheng, Chan-Chi Jason, Singh, Satwant, Garg, Manish, Shen, Ju, Agrawal, Om
• Primary Examiner(s): LE, DON P
• Application Number:
  US11/200,983
• Time in Patent Office: 826 Days
• Field of Search: 326 37- 41, 326/46
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

In one embodiment of the invention, a programmable logic block within a programmable logic device includes: a plurality of lookup tables, each lookup table providing a combinatorial output signal; and a plurality of registers, each register being adapted to register a selected one of the combinatorial output signals, wherein the number of registers is less than the number of lookup tables.

Claims

1. A programmable logic block within a programmable logic device, comprising:

a plurality of interconnected slices, each slice including;

a plurality of interconnected lookup tables, each lookup table being adapted to receive input signals from a routing structure and being adapted to provide a combinatorial output signal; and

a plurality of registers, each register being adapted to register a selected one of the combinatorial output signals,

wherein the number of registers in at least one slice of the programmable logic block is no more than half the number of lookup tables in the at least one slice.

2. The programmable logic block of claim 1 further comprising a three-to-one multiplexer within the at least one slice, the three-to-one multiplexer being adapted to select between the combinatorial output signals from a pair of the lookup tables and a data input signal and to provide the selected signal to one of the registers.

3. The programmable logic block of claim 1 further comprising a two-to-one multiplexer within the at least one slice, the two-to-one multiplexer being adapted to select between the combinatorial output signal from one of the lookup tables and a data input signal and to provide the selected signal to one of the registers.

4. The programmable logic block of claim 1, wherein:

the number of slices is four;

the number of lookup tables in each slice is two; and

the number of registers in the at least one slice is zero.

5. The programmable logic block of claim 1, wherein:

the number of slices is four;

the number of lookup tables in each slice is two; and

the number of registers in each at least one slice is one.

6. The programmable logic block of claim 1, wherein:

the number of slices is four;

the number of lookup tables in each slice is two; and

the number of registers in each slice is one.

7. The programmable logic block of claim 1, wherein:

the number of slices is at least two;

the number of lookup tables in each slice is four; and

the number of registers in the at least one slice is zero.

8. The programmable logic block of claim 1, wherein:

the number of slices is at least two;

the number of lookup tables in each slice is four; and

the number of registers in the at least one slice is two.

9. A programmable logic device, comprising:

a plurality of programmable logic blocks, wherein each programmable logic block includes a plurality of slices, each slice including a plurality of lookup tables, each lookup table providing a combinatorial output signal, and wherein each programmable logic block includes a plurality of registers, each register being adapted to register a selected one of the combinatorial output signals, wherein for at least one of the programmable logic blocks the number of lookup tables is sixteen and the number of registers is no more than twelve.

10. The programmable logic block of claim 9, wherein the number of lookup tables is sixteen and the number of registers is eight.

11. A programmable logic block within a programmable logic device, comprising:

a plurality of slices, wherein each slice includes a plurality of lookup tables, each lookup table being adapted to provide a combinatorial output signal, the slices including a plurality of registers adapted to register corresponding ones of the combinatorial output signals, and wherein in at least one slice the number of registers is less than the number of lookup tables.

12. The programmable logic block of claim 11, wherein at least one of the slices contains no registers.

13. The programmable logic block of claim 11, wherein at least one of the slices includes two lookup tables and a single register, the single register being adapted to register a combinatorial output from only one of the two lookup tables.

14. The programmable logic block of claim 11, wherein at least one of the slices includes two lookup tables and a single register, the single register being adapted to register a combinatorial output from either one of the two lookup tables.

15. The programmable logic block of claim 11, wherein a first one of the slices includes two lookup tables and two corresponding registers, each register being adapted to register a combinatorial output from the corresponding lookup tables, and wherein a second one of the slices includes two lookup tables and no corresponding registers.

16. The programmable logic block of claim 11, wherein at least one of the slices includes four lookup tables and two registers, wherein a first one of the two registers is adapted to register a combinatorial output from only a first one of the four lookup tables, and wherein a second one of the two registers is adapted to register a combinatorial output from only a second one of the four lookup tables.

17. The programmable logic block of claim 16, wherein a second one of the slices includes four lookup tables and no corresponding registers.

18. The programmable logic block of claim 11, wherein at least one of the slices includes four lookup tables and two registers, wherein a first one of the two registers is adapted to register a combinatorial output from either a first one and a second one of the four lookup tables, and wherein a second one of the two registers is adapted to register a combinatorial output from either a third one and a fourth one of the four lookup tables.

19. The programmable logic block of claim 18, wherein a second one of the slices includes four lookup tables and no corresponding registers.

20. The programmable logic block of claim 11, wherein at least one of the slices includes four lookup tables and no corresponding registers.