Method and circuit for rapid alignment of signals
First Claim
1. A method for aligning a first signal with a second signal, comprising:
- creating two or more shifted copies of the second signal; and
determining which of the shifted copies of the second signal are substantially aligned with the first signal,wherein the two or more copies of the second signal are each shifted by one or more cycles of a clock signal, the clock signal being of higher frequency than a frequency of the second signal.
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Accused Products
Abstract
Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.
84 Citations
18 Claims
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1. A method for aligning a first signal with a second signal, comprising:
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creating two or more shifted copies of the second signal; and determining which of the shifted copies of the second signal are substantially aligned with the first signal, wherein the two or more copies of the second signal are each shifted by one or more cycles of a clock signal, the clock signal being of higher frequency than a frequency of the second signal. - View Dependent Claims (2, 4, 5, 6, 7, 8, 9)
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3. A method for aligning a first signal with a second signal, comprising:
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creating two or more shifted copies of the second signal; and determining which of the shifted copies of the second signal are substantially aligned with the first signal, wherein the creating operation further comprises;
providing a shift register having an input receiving the second signal and a clock input receiving a clock signal, the clock signal being of higher frequency than a frequency of the second signal, the shift register having two or more outputs, each output including a copy of the second signal shifted by one or more cycles of the clock signal.
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10. A circuit for aligning two or more signals including a first and second signal, the circuit comprising:
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a shift register generating two or more shifted copies of the second signal; a plurality of phase detectors, each phase detector receiving the first signal and receiving one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal; and a multiplexer receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. - View Dependent Claims (12, 14, 15, 16)
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11. A circuit for aligning two or more signals including a first and second signal, the circuit comprising:
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a shift register generating two or more shifted copies of the second signal; and a plurality of phase detectors, each phase detector receiving the first signal and receiving one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal, wherein the shift register has an input receiving the second signal and a clock input receiving a clock signal, the clock signal being of higher frequency than a frequency of the second signal, the shift register having two or more outputs, each output including a copy of the second signal shifted by one or more cycles of the clock signal.
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13. A circuit for aligning two or more signals including a first and second signal, the circuit comprising:
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a shift register generating two or more shifted copies of the second signal; and a plurality of phase detectors, each phase detector receiving the first signal and receiving one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal, wherein the two or more copies of the second signal are each shifted by one or more cycles of a clock signal, the clock signal being of higher frequency than a frequency of the second signal.
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17. An integrated circuit, comprising:
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a circuit section for aligning two or more signals including a first and second signal, the circuit section comprising; a shift register generating two or more shifted copies of the second signal; a plurality of phase detectors, each phase detector receiving the first signal and receiving one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal; and a multiplexer receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. - View Dependent Claims (18)
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Specification