Adaptive predistortion for a transmit system
First Claim
1. A preprogrammed control device for use in controlling an adaptive predistortion subsystem, said device being programmed to operate in a plurality of states associated with sets of commands to be executed by said subsystem in response to said device being in said states, the device comprising:
- a processor means for receiving and processing data;
first memory means for storing said data; and
second memory means for storing preprogrammed settings for said device, whereinsaid device is adapted to transition from a first one of said states to a second one of said states in response to detection of at least one of a set of conditions based, at least in part, on said processed data.
3 Assignments
0 Petitions
Accused Products
Abstract
Systems, methods, and devices relating to the provision of deliberate predistortion to an input signal to compensate for distortions introduced by an amplifier subsystem. An input signal is received by a signal processing system which includes a predistortion subsystem. The input signal is decomposed and the fragments are then predistorted by the predistortion subsystem by applying a deliberate predistortion to the fragments. The predistorted fragments are then separately processed and recombined to arrive at the system output signal. The predistortion subsystem adaptively adjusts based on characteristics of the system output signal. Also, the predistortion subsystem is equipped with a control system that is state based—the state of the predistortion subsystem is dependent upon the prevailing conditions and, when required, the control system switches the state of the predistortion subsystem. A feedback signal, a replica of the system output signal, is used in updating lookup table entries used to determine the predistortion.
23 Citations
36 Claims
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1. A preprogrammed control device for use in controlling an adaptive predistortion subsystem, said device being programmed to operate in a plurality of states associated with sets of commands to be executed by said subsystem in response to said device being in said states, the device comprising:
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a processor means for receiving and processing data; first memory means for storing said data; and second memory means for storing preprogrammed settings for said device, wherein said device is adapted to transition from a first one of said states to a second one of said states in response to detection of at least one of a set of conditions based, at least in part, on said processed data. - View Dependent Claims (2, 3, 4, 5, 34)
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6. A programmable control device capable of controlling a predistortion subsystem for a transmission system, the programmable control device being programmable to operate in a plurality of states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem in response to the programmable control device being in an associated state, the programmable control device comprising:
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a processor capable of processing data relating to a status of the predistortion subsystem; and a memory circuit capable of storing settings for the programmable control device; wherein, responsive to the processed data, said processor is adapted to transition from one of said states to another of said states based at least in part on the settings of said memory circuit. - View Dependent Claims (7, 8, 9, 10, 11, 12, 35)
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13. An article of manufacture, comprising:
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a storage medium having instructions stored thereon which, if executed are capable of causing a programmable control device to control a predistortion subsystem for a transmission system, the programmable control device being programmed to operate in a plurality of states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem in response to the programmable control device being in an associated state, by; processing data relating to a status of the predistortion subsystem; storing settings for the programmable control device; and responsive to the processed data, transitioning the preprogrammed control device from one of said states to another of said states based at least in part on the stored settings. - View Dependent Claims (14, 15, 16, 17, 18, 19, 36)
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20. An application specific integrated circuit capable of controlling a predistortion subsystem of a transmission system, the application specific integrated circuit being programmable to operate in a plurality of states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem in response to the application specific integrated circuit being in an associated state, the application specific integrated circuit comprising:
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a processor capable of processing data relating to a status of the predistortion subsystem; and a memory circuit capable of storing settings for the application specific integrated circuit; wherein, responsive to the processed data, the processor is adapted to cause the application specific integrated circuit to transition from one of said states to another one of said states based at least in part on the settings of said memory circuit. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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27. A combinational logic circuit capable of controlling a predistortion subsystem of a transmission system, the combinational logic circuit being programmable to operate in a plurality of states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem in response to the combinational logic circuit being in an associated state, the combinational logic circuit comprising:
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a first logic circuit capable of processing data relating to a status of the predistortion subsystem; and a second logic circuit capable of storing settings for the combinational logic circuit; wherein, responsive to the processed data, the first logic circuit is adapted to cause the combinational logic circuit to transition from one of said states to another one of said states based at least in part on the settings of said second logic circuit. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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Specification