Eight transistor SRAM cell with improved stability requiring only one word line

• US 7,295,458 B2
• Filed: 01/18/2006
• Issued: 11/13/2007
• Est. Priority Date: 01/18/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuen H., Plass, Donald W., Huott, William V.
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Luu; Pho M.
• Application Number:
  US11/334,647
• Publication Number:
  US 20070165445A1
• Time in Patent Office: 664 Days
• Field of Search: 365/154, 365155-156, 365/190
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

Claims

1. A static random access memory comprising in combination:

a plurality of bi-stable memory cells arranged in rows and columns;

each of said plurality of memory cells includes a first pull-up transistor and a first pull-down transistor coupled in series between a supply voltage and common and cross coupled with a second pull-transistor and a second pull-down transistor connected in series between said supply voltage and common, and with a first node between said first pull-up transistor and said second pull-down transistor and a second node between said second pull-up transistor and said second pull-down transistor;

cells in a column each connected via a pair of write access devices to a pair of write bit lines for writing data into said cell;

said cells in a column each connected via a read access device to a read bit line, separate from said pair of write bit lines, for reading data from said cell; and

cells in a row each connected via a word line access device to a single word line;

whereby activation to respective predetermined states of said word line and said pair of write bit lines writes data to said cell and activation of said word line and said read bit line reads data from said cell.

2. A static random access memory as in claim 1, wherein said pair of write access devices are coupled respectively between said pair of write bit lines and said first and said second node and said read access device is connected between said read bit line and said first node.

3. A static random access memory as in claim 2, wherein said pair of write access devices are each an FET, said read access device is an FET and said word line access device is an FET.

4. A static random access memory as in claim 2, wherein said pair of write access devices are each an NFET, said read access device is an NFET and said word line access device is an NFET with the drains of said write access devices and the drain of said read access device connected to the source of said word line access device.

5. A static random access memory as in claim 1, wherein said pair of write access devices are each an NFET, said read access device is an NFET and said word line access device is an NFET with the drains of said write access devices and the drain of said read access device connected to the source of said word line access device.

6. A static random access memory as in claim 1, wherein said pair of write access devices are each an NFET, said read access device is an NFET and said word line access device is an NFET with the drains of said write access devices and the drain of said read access device connected to the source of said word line access device.

7. A static random access memory comprising in combination:

a plurality of bi-stable memory means arranged in rows and columns;

each of said plurality of bi-stable memory means includes a first pull-up transistor and a first pull-down transistor coupled in series between a supply voltage and common and cross coupled with second pull-transistor and a second pull-down transistor connected in series between said supply voltage and common and with a first node between said first pull-up transistor and said second pull-down transistor and a second node between said second pull-up transistor and said second pull-down transistor;

said memory means in a column each coupled to write access means for writing data into said cell;

said memory means in a column each connected a read access means separate from write access for reading data from said cell; and

said memory means in a row each coupled to a word line access;

whereby activation to respective predetermined states of said word line means and said write access means writes data to said cell and activation of said word line means and said read access means reads data from said cell.

8. A static random access memory as in claim 7, wherein said write access means includes a pair of FETs coupled respectively between said pair of write bit lines and said first node and said second node and said read access means includes an FET connected between said read bit line and said first node.

9. A static random access memory as in claim 8, wherein said write access includes a pair of NFETs, said read access means is an NFET and said word line access means is an NFET with the drains of said write access NFETs and the drain of said read access NFET connected to the source of said word line NFET.

10. A static random access memory as in claim 7, wherein said write access includes a pair of NFETs, said read access means is an NFET and said word line access means is an NFET with the drains of said write access NFETs and the drain of said read access NFET connected to the source of said word line NFET.

11. A static random access memory as in claim 10, wherein said write access includes a pair of NFETs, said read access means is an NFET and said word line access means is an NFET with the drains of said write access NFETs and the drain of said read access NFET connected to the source of said word line NFET.