xDSL function ASIC processor and method of operation

• US 7,295,571 B2
• Filed: 01/12/2006
• Issued: 11/13/2007
• Est. Priority Date: 03/01/2000
• Status: Expired due to Term

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Primary Examiner(s): Levitan; Dmitry
• Application Number:
  US11/330,610
• Publication Number:
  US 20060203843A1
• Time in Patent Office: 670 Days
• Field of Search: 370/392, 370/401, 370/464, 370/465, 370537-539, 710/20, 710/100, 710/260, 710/266, 709/230, 709/232
• US Class Current: 370/464
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An improved type of application-specific integrated circuit block (ASIC) is disclosed that is optimized for use in a communications system, and is somewhat programmble through the use of particular data objects that can specify an instruction and operand for the ASIC. The ASIC can be multi-tasking to perform multiple receive or transmit operations, two different kinds of transmit or receive operations, and operaions for mulitple ports. The ASIC generally uses an input data decoder block for decoding an input data object; a computation logic block for performing application specific computations in connection with the input data object, and an output data encoder block for encoding an output data object based on the specific computations. Using a common memory, a set of such ASICs can be arranged in a form of logical (or logical hybrid) pipeline.

Claims

1. A communication device comprising first and second communication ports, the device to process a first sequence of channel symbols associated with the first communication port and a second sequence of channel symbols associated with the second communication port:

a memory to store a first data object comprising a data portion associated with the first sequence of channel symbols and a parameter portion associated with configuring processing circuitry, and to store a second data object comprising a data portion associated with the second sequence of channel symbols and a parameter portion associated with computations performed by the processing circuitry;

a first functional unit to process the data portion associated with the first sequence of channel symbols in accordance with the parameter portion of the first data object; and

a second functional unit to process the data portion associated with the second sequence of channel symbols in accordance with the parameter portion of the second data object, wherein the first and second functional units form pipeline processing stages.

2. The communication device as set forth in claim 1, further comprising:

a bus coupled to the memory; and

at least one scheduler to receive the first data object from the memory and to provide the first data object to the first functional unit via the bus.

3. The communication device as set forth in claim 2, wherein the first functional unit generates the second data object using the first data object.

4. The communication device as set forth in claim 3, wherein the communication device processes the first data object according to an ordered set of processing steps, wherein the first functional unit processes the first data object according to a first processing step in the ordered set of processing steps, wherein after the first data object has been processed by the first functional unit the first data object is processed by the second functional unit according to a second processing step immediately following the first processing step in the ordered set of processing steps.

5. The communication device as set forth in claim 4, wherein the second functional unit is a programmable processor to receive the second data object from the memory.

6. The communication device as set forth in claim 4, wherein the first and second sequences of channel symbols include discrete multi-tone symbols.

7. The communication device as set forth in claim 6, wherein the first functional unit is configured to process the first data object to provide QAM (quadrature-amplitude-modulation) decoding of the data portion of the first data object.

8. The communication device as set forth in claim 6, wherein the first functional unit is configured to process the first data object to provide QAM (quadrature-amplitude-modulation) encoding of the data portion of the first data object.

9. The communication device as set forth in claim 2, wherein the second functional unit is a programmable processor to receive the second data object from the memory.

10. The communication device as set forth in claim 2, wherein the at least one scheduler includes a scheduler associated with one of a transmission convergence layer or a physical media dependent layer.

11. The communication device as set forth in claim 2, wherein the at least one scheduler includes at least one of transmission convergence scheduler and a physical media dependent scheduler.

12. The communication device as set forth in claim 2, wherein the communication device is formed as a single integrated circuit.

13. The communication device as set forth in claim 2, wherein the bus is a time domain multiplexed bus coupled to an analog front end circuit associated with at least one of a transceiver and a coder-decoder (CODEC).

14. The communication device as set forth in claim 13, wherein the analog front end circuitry includes a transceiver and the bus is at least n-bits wide in each of transmit and receive directions, where n is greater than or equal to two.

15. The communication device as set forth in claim 1, wherein the first port is configured to receive the first sequence of channel symbols and the second port is configured to receive the second sequence of channel symbols.

16. The communication device as set forth in claim 1, wherein the first port is configured to receive the first sequence of channel symbols and the second port is configured to transmit the second sequence of channel symbols.

17. The communication device as set forth in claim 1, wherein the first functional unit is configured to process the first data object to provide QAM (quadrature-amplitude-modulation) decoding of the data portion of the first data object.

18. The communication device as set forth in claim 1, wherein the first functional unit is configured to process the first data object to provide QAM (quadrature-amplitude-modulation) encoding of the data portion of the first data object.

19. The communication device as set forth in claim 1, wherein the parameter portion of the second data object comprises a symbol sequence number indicative of the sequence of channel symbols associated with the data portion of the second data object.

20. The communication device as set forth in claim 19, wherein the symbol sequence number is associated with a discrete multi-tone protocol.

21. The communication device as set forth in claim 1, wherein each of the first an second communication ports are configured to support an xDSL standard using less than approximately 1,400,000 transistors in combination.

22. The communication device as set forth in claim 1, wherein the communication device is formed as a single integrated circuit.

23. The communication device as set forth in claim 1, wherein the pipeline stages are configured to uses a common pipeline clock.

24. The communication device as set forth in claim 23, wherein the common pipeline clock is configured to operate at a rate greater than a clock rate used for first and second communication ports when in communication with a remote transceiver.

25. The communication device as set forth in claim 23, wherein the pipeline clock is configured to operate at a rate greater than a multi-tone symbol rate, T, where T is the baud rate.

26. A system comprising:

first and second communication pods, the device to process a first sequence of channel symbols associated with the first communication port and a second sequence of channel symbols associated with the second communication port;

a memory to store a first data object comprising a data portion associated with the first sequence of channel symbols and a parameter portion associated with control and/or configuring processing circuitry, and to store a second data object comprising a data portion associated with the second sequence of channel symbols and a parameter portion associated with computations performed by the processing circuitry;

a first processing module to process the data portion associated with the first sequence of channel symbols in accordance with the parameter portion of the first data object;

a second processing module to process the data portion associated with the second sequence of channel symbols in accordance with the parameter portion of the second data object, wherein the first and second processing modules form stages of a pipeline processor; and

at least one scheduler coupled to at least one of the first and the second processing modules, the scheduler configured to support signals associated with an xDSL standard.

27. The system of claim 26, wherein the at least one scheduler includes at least one of a transmission convergence layer scheduler and a physical media dependent layer scheduler.

28. The system of claim 27, wherein at least one of the transmission convergence layer scheduler and a physical media dependent layer scheduler is configured to perform a transmit operation and a receive operation during a single discrete multi-tone symbol operating cycle.

29. The system of claim 26, wherein the pipeline processor includes M additional stages, each of the M stages comprising at least one processing module.

30. The system of claim 29, wherein at least the M additional stages are configured to uses a common pipeline clock.

31. The system of claim 30, wherein the n independent communication ports are configured to support the xDSL standard using less than approximately (M+2)×

700,000 transistors in combination.

32. The system of claim 29, wherein each M additional stage of the pipeline processor and each of the first and second processing modules support n independent communication ports, and wherein N distinct operations performed on a discrete multi-tone symbol is such that the number of stages (M+2)<

n×

N.