Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link

• US 7,295,578 B1
• Filed: 09/12/2001
• Issued: 11/13/2007
• Est. Priority Date: 09/12/2001
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Lyle, James D., Kim, Gyudong, Kim, Min-Kyu, Tan, Ken-Sue, Wolf, Paul Daniel, Pham, Long Van, Martin, Russel A.
• Primary Examiner(s): Phunkulh, Bob A.
• Application Number:
  US09/954,291
• Time in Patent Office: 2,253 Days
• Field of Search: None
• US Class Current: 370/503
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/435 Processing of additional data, e.g. decrypting of additional data, reconstructing software from modules extracted from the transport stream

Abstract

A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver and auxiliary data are transmitted from the receiver to the transmitter (or from the transmitter to the receiver and also from receiver to the transmitter), a transmitter or receiver for use in such a system, and methods for sending auxiliary data and video data over such a link, synchronizing such auxiliary data with such video data, and generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted. Typically, the auxiliary data include one or more streams of audio data. In some embodiments the transmitter transmits a video clock to the receiver over a video clock channel, at least one of the transmitter and receiver transmits at least one stream of auxiliary data to the other one of the transmitter and the receiver, and at least one of the transmitter and the receiver transmits over the video clock channel at least one auxiliary clock for the auxiliary data.

Claims

1. A communication system, including:

a receiver;

a transmitter; and

a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over one or more channels of the link, at least one of the transmitter and the receiver is configured to transmit at least one stream of auxiliary data to the other one of the transmitter and the receiver over one or more channels of the link, the transmitter is configured to transmit a video clock to the receiver over a video clock channel of the link, and said at least one of the transmitter and the receiver is also configured to transmit, to the other one of the transmitter and the receiver, at least one auxiliary clock for the auxiliary data over said video clock channel.

2. The system of claim 1, wherein the transmitter is configured to transmit to the receiver at least some of the auxiliary data discontinuously over a first channel of the link while continuously transmitting the video clock and each said auxiliary clock over the video clock channel.

3. The system of claim 1, wherein the transmitter is configured to transmit to the receiver a binary signal over the video clock channel, and the binary signal has periodic features that determine the video clock and data structures that determine each said auxiliary clock.

4. The system of claim 3, wherein the periodic features are periodically occurring rising edges of the binary signal, the data structures are falling edges of the binary signal, and a time interval between each of the falling edges and a preceding one of the rising edges determines each said auxiliary clock.

5. The system of claim 3, wherein the video clock has frequency f, and the auxiliary clock has frequency f2=f/N, where N is an integer.

6. The system of claim 3, wherein each of the data structures is indicative of at least two precise times following one of the periodic features, whereby the binary signal determines at least two auxiliary clocks.

7. The system of claim 1, wherein at least some of the auxiliary data are audio data.

8. A transmitter for use in data transmission over a serial link, wherein the link is configured to transmit digital video data and has at least one other characteristic of a transition minimized differential signaling link, said transmitter including:

a video input for receiving video data;

an auxiliary data input for receiving auxiliary data;

outputs configured to be coupled to channels of the link, including a first output configured to be coupled to a clock channel of the link; and

circuitry, coupled to the video input, the auxiliary data input, and at least some of the outputs including the first output, configured to assert output signals indicative of the auxiliary data and the video data to the outputs, and configured to assert a clock signal to the first output, wherein the clock signal is indicative of a video clock and at least one auxiliary clock for the auxiliary data.

9. The transmitter of claim 8, wherein the clock signal is a binary signal having periodic features that determine the video clock and data structures that determine each said auxiliary clock.

10. The transmitter of claim 9, wherein each of the data structures is indicative of at least two precise times following one of the periodic features, whereby the binary signal determines at least two auxiliary clocks.

11. A communication system, including:

a receiver;

a transmitter; and

a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over a first channel of the link and at least one of the transmitter and the receiver is configured to transmit a binary signal to the other of the transmitter and the receiver over a second channel of the link, wherein the binary signal has periodic features that determine a pixel clock for the video data, and the binary signal determines a stream of data structures indicative of at least one stream of audio data and at least one additional clock for the at least one audio data stream.

12. The system of claim 11, wherein at least one of the transmitter and the receiver is configured to transmit at least one signal indicative of said at least one audio data stream to the other of the transmitter and the receiver over a channel of the link other than said second channel.

13. A communication system, including:

a receiver;

a transmitter; and

a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over a first channel of the link and at least one of the transmitter and the receiver is configured to transmit a binary signal to the other of the transmitter and the receiver over a second channel of the link, wherein the binary signal has periodic features that determine a pixel clock for the video data, and the binary signal determines a stream of data structures indicative of at least two streams of auxiliary data, wherein the stream of data structures is also indicative of at least two additional clocks, and each of the additional clocks is for a different stream of auxiliary data.

14. The system of claim 13, wherein each of at least some of the data structures includes data and a header identifying which of the auxiliary data streams includes the data.

15. The system of claim 13, wherein each of at least some of the data structures includes fine position data indicative of a time interval commencing on occurrence of a preceding one of the periodic features, and a header identifying which of the auxiliary data streams includes the fine position data.

16. The system of claim 13, a data structure of each of at least some of the data structures includes fine position data indicative of a time interval commencing on occurrence of a reference feature of said data structure, coarse position data indicative of a time interval between the occurrence of the reference feature and a preceding one of the periodic features, and a header identifying which of the auxiliary data streams includes the fine position data.

17. A communication system, including:

a receiver;

a transmitter; and

a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over a first channel of the link and to transmit a binary signal to the receiver over a second channel of the link, wherein the binary signal has periodically occurring edges of a first type, the periodically occurring edges determine a video clock, the binary signal has edges of a second type, and relative timing between the edges of the second type and the edges of the first type is indicative of at least one of a stream of audio data, a clock for a stream of audio data, and a clock for each of at least two streams of auxiliary data, wherein the relative timing between the edges of the second type and the edges of the first type is indicative of a clock for a stream of audio data.

18. The system of claim 17, wherein the relative timing between the edges of the second type and the edges of the first type is also indicative of a second clock for another stream of auxiliary data.

19. A receiver for coupling to a serial link, for use in a system including the link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

a frequency synthesizer to generate, from a recovered version of the video clock, an auxiliary clock for the auxiliary data, wherein the auxiliary clock has a time-averaged frequency f_au, wherein the frequency synthesizer includes a phase locked loop, and the phase locked loop includes;

a voltage controlled oscillator having an output at which the auxiliary clock is asserted; and

a dual-modulus frequency divider coupled to receive the auxiliary clock and configured to divide the frequency of the auxiliary clock by a selectable value L to generate a second clock, where L is a selected one of a first integer N and a second integer P, and the second clock has frequency f/M′

, where M′

is a number, wherein the dual-modulus frequency divider is configured to operate cyclically to divide the frequency of the auxiliary clock by the first integer N and then by the second integer P, with a duty cycle that is controlled so that the time-averaged frequency of the second clock is equal to (Q/M)f, where Q has a predetermined value greater than N and less than P.

20. The receiver of claim 19, wherein P=N+1.

21. The receiver of claim 19, also including:

circuitry for generating a set of L recovered clocks, wherein each of the recovered clocks has the frequency f, is a recovered version of the video clock, wherein and has a different phase φ

=φ

₀+2π

(k/L), where k is a non-negative integer in the range {0, . . . , L−

1}; and

an edge-combining fractional divider, coupled and configured to receive any selected one of the recovered clocks, and to output a third clock having frequency ((M+k)/L)f in response to said selected one of the recovered clocks, where M is an integer, and wherein the phase locked loop also includes;

a phase detector, coupled to receive the second clock and the third clock, and configured to generate a phase signal indicative of relative phase of the second clock and the third clock in response to said second clock and said third clock; and

a loop filter coupled to receive the phase signal and configured to generate an error signal in response to the phase signal, wherein the voltage controlled oscillator is coupled to receive the error signal and configured to generate the auxiliary clock in response to said error signal.

22. A receiver for coupling to a serial link, for use in a system including the link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

a frequency synthesizer to generate, from a recovered version of the video clock, an auxiliary clock for the auxiliary data, wherein the auxiliary clock has a time-averaged frequency f_au; and

a second frequency divider coupled and configured to receive the recovered version of the video clock and to output a third clock having frequency f/M in response to the recovered version of the video clock, where M is an integer, and wherein the frequency synthesizer includes a phase locked loop, and the phase locked loop includes;

a voltage controlled oscillator having an output at which the auxiliary clock is asserted; and

a dual-modulus frequency divider coupled to receive the auxiliary clock and configured to divide the frequency of the auxiliary clock by a selectable value L to generate a second clock, where L is a selected one of a first integer N and a second integer P, and the second clock has frequency f/M′

, where M′

is a number;

a phase detector, coupled to receive the second clock and the third clock, and configured to generate a phase signal indicative of relative phase of the second clock and the third clock in response to said second clock and said third clock; and

a loop filter coupled to receive the phase signal and configured to generate an error signal in response to the phase signal, wherein the voltage controlled oscillator is coupled to receive the error signal and configured to generate the auxiliary clock in response to said error signal.

23. A receiver for use in a system including a serial link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

a frequency synthesizer configured to generate, from a recovered version of the video clock, an auxiliary clock for the auxiliary data, wherein the auxiliary clock has a time-averaged frequency f_au, and the frequency synthesizer includes;

a dual-modulus frequency divider coupled and configured to receive the recovered video clock and to divide the frequency of the recovered video clock by a selectable value Q to generate a first clock, where Q is a selected one of a first integer R and a second integer S;

a phase detector, coupled to receive the first clock and a second clock, and configured to generate a phase signal indicative of relative phase of the first clock and the second clock in response to said first clock and said second clock;

a loop filter coupled to receive the phase signal and configured to generate an error signal in response to the phase signal;

a voltage controlled oscillator, coupled to receive the error signal, and configured to generate the auxiliary clock in response to said error signal; and

a second dual-modulus frequency divider coupled to receive the auxiliary clock and configured to divide the frequency of the auxiliary clock by a second selectable value L to generate the second clock, where L is a selected one of a third integer N and a fourth integer P.

24. The receiver of claim 23, wherein the dual-modulus frequency divider is configured to operate cyclically to divide the frequency of the recovered video clock by the first integer R and then the second integer S, with a duty cycle that is controlled to so that the first clock has a time-averaged frequency f₁=f/T′

, where T′

has a predetermined value greater than R and less than S, and

wherein the second dual-modulus frequency divider is configured to operate cyclically to divide the frequency of the auxiliary clock by the third integer N and then by the fourth integer P, with a duty cycle that is controlled to so that the second clock has a time-averaged frequency f₂=f_au/U′

, where U′

has a predetermined value greater than N and less than P.

25. The receiver of claim 24, wherein S=R+1 and wherein P=N+1.

26. A receiver for use in a system including a serial link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

circuitry for generating a set of L recovered clocks, wherein each of the recovered clocks has the frequency f, is a recovered version of the video clock, and has a different phase φ

=φ

₀+2π

(m/L), where m is a non-negative integer in the range {0, . . . , L−

1};

a multiplexer and a preload counter coupled to the multiplexer, wherein each of the multiplexer and the preload counter is coupled to receive any selected one of the recovered clocks, and the multiplexer is configured to output a first clock having frequency (1±

k/ML)f in response to said selected one of the recovered clocks, where k and M are integers; and

a dual-modulus frequency divider coupled to receive the first clock and configured to divide the frequency of the first clock by a selectable value L to generate an auxiliary clock for the auxiliary data, where L is a selected one of a first integer N and a second integer P.

27. The receiver of claim 26, wherein the dual-modulus frequency divider is configured to operate cyclically to divide the frequency of the auxiliary clock by the first integer N and then by the second integer P, with a duty cycle that is controlled so that auxiliary clock has time-averaged frequency equal to (Q/(1±

k/ML))f, where Q has a predetermined value greater than N and less than P.

28. A receiver for use in a system including a serial link and a transmitter configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, the video data are transmitted at a video data rate, and packets of the auxiliary data are transmitted at an auxiliary data rate, said receiver including:

rate determination circuitry coupled to receive time stamp data transmitted to the receiver over the link and configured to generate a rate signal indicative of the auxiliary data rate in response to the time stamp data, wherein the time stamp data are indicative of times at which the packets of the auxiliary data were transmitted by the transmitter; and

auxiliary clock generation circuitry coupled and configured to receive the rate signal and to generate an auxiliary clock having frequency closely matching the auxiliary data rate in response to the rate signal.

29. A communication system, including:

a receiver;

a transmitter; and

a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the video data are transmitted at a video data rate, and packets of the auxiliary data are transmitted at an auxiliary data rate, and wherein the receiver comprises;

rate determination circuitry coupled to receive time stamp data transmitted to the receiver over the link and configured to generate a rate signal indicative of the auxiliary data rate in response to the time stamp data, wherein the time stamp data are indicative of times at which the packets of the auxiliary data were transmitted by the transmitter; and

auxiliary clock generation circuitry coupled and configured to receive the rate signal and to generate an auxiliary clock having frequency closely matching the auxiliary data rate in response to the rate signal.

30. The system of claim 29, wherein the auxiliary data are audio data.

31. The system of claim 29, wherein the transmitter is also configured to transmit a counter clock over at least one channel of the link, and the receiver is configured to recover the counter clock thereby generating a recovered counter clock, and the auxiliary clock generation circuitry is configured to generate the auxiliary clock in response to the recovered counter clock and the rate signal.

32. A receiver for use in a system including a serial link and a transmitter configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, the video data are transmitted at a video data rate, and packets of the auxiliary data are transmitted at an auxiliary data rate, said receiver including:

rate determination circuitry coupled to receive a rate signal transmitted to the receiver over the link and configured to generate a recovered rate signal indicative of the auxiliary data rate in response to the rate signal, wherein the rate signal is indicative of the auxiliary data rate at which the packets of the auxiliary data were transmitted by the transmitter; and

auxiliary clock generation circuitry coupled and configured to receive the recovered rate signal and to generate an auxiliary clock having frequency closely matching the auxiliary data rate in response to the recovered rate signal.

33. A receiver for use in a system including a serial link and a transmitter configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, the video data are transmitted at a video data rate, and the auxiliary data are transmitted at an auxiliary data rate, said receiver including auxiliary clock generation circuitry for generating an auxiliary clock whose frequency closely matches the auxiliary data rate, said auxiliary clock generation circuitry including:

a memory structure coupled and configured to queue up packets of the auxiliary data that have been transmitted to the receiver over the link; and

rate determination circuitry configured to generate an average time difference signal for each sequence of L of the packets queued in the memory structure, each said average time difference signal being indicative of an average time delay equal to (Et(1)+Et(2)+ . . . +Et(L))/L, where Et(n) is a time difference between arrival time at the memory structure of the n-th one of the packets in the sequence and arrival time at the memory structure of the (n−

1)th one of the packets in the sequence.

34. The receiver of claim 33, wherein L is a power of two.

35. A receiver for use in a system including a serial link and a transmitter configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, the video data are transmitted at a video data rate, and the auxiliary data are transmitted at an auxiliary data rate, said receiver including auxiliary clock generation circuitry for generating an auxiliary clock whose frequency closely matches the auxiliary data rate, said auxiliary clock generation circuitry including:

a memory structure coupled and configured to queue up packets of the auxiliary data that have been transmitted to the receiver over the link, each of the packets including a time stamp indicative of one of an absolute transmission time and a relative transmission time of said each of the packets; and

rate determination circuitry configured to generate an average time delay signal for each sequence of L of the packets queued in the memory structure by processing the time stamp of each of the packets in the sequence, each said average time delay signal being indicative of average time delay between transmission of successively transmitted ones of the packets in the sequence.

36. The receiver of claim 35, wherein each said time stamp is indicative of a time interval between transmission of said each of the packets and transmission of a previously transmitted one of the packets.

37. A receiver for use in a system including a serial link and a transmitter configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, the video data are transmitted at a video data rate, and the auxiliary data are transmitted at an auxiliary data rate, said receiver including auxiliary clock generation circuitry for generating an auxiliary clock whose frequency closely matches the auxiliary data rate, said auxiliary clock generation circuitry including:

FIFO circuitry including a FIFO memory, wherein the FIFO circuitry is coupled and configured to queue in the FIFO memory packets of the auxiliary data that have been transmitted to the receiver over the link, and to clock the packets out of the FIFO memory at a clock frequency determined by varying a reference frequency in response to a feedback signal, wherein at any instant during operation of said FIFO circuitry the FIFO memory is filled up to a FIFO level with a number of said packets; and

feedback circuitry coupled to the FIFO circuitry and configured to generate the feedback signal, wherein said feedback signal is indicative of at least one of the FIFO level and a rate of change of the FIFO level.

38. The receiver of claim 37, wherein the FIFO circuitry is configured to increase the clock frequency in response to the feedback signal indicating that the FIFO level is greater than a threshold level.

39. The receiver of claim 37, wherein the FIFO circuitry is configured to operate in a first mode in response to the feedback signal indicating that the FIFO level is greater than a first threshold level but less than a second threshold level, wherein the second threshold level is greater than the first threshold level, and the FIFO circuitry is configured to operate in a second mode in response to the feedback signal indicating that the FIFO level is greater than the second threshold level.

40. The receiver of claim 39, wherein the FIFO circuitry is configured to operate in a third mode in response to the feedback signal indicating that the FIFO level is less than the first threshold level.

41. The receiver of claim 37, wherein the FIFO circuitry is configured to change the clock frequency at a rate which depends on a difference between the FIFO level and a threshold level as indicated by the feedback signal.

42. The receiver of claim 41, wherein said rate depends nonlinearly on the difference between the FIFO level and a threshold level as indicated by the feedback signal.

43. The receiver of claim 37, wherein the FIFO circuitry is configured to change the clock frequency in a manner that depends on the rate of change of the FIFO level as indicated by the feedback signal.

44. The receiver of claim 37, wherein the FIFO circuitry includes:

first circuitry for generating a raw feedback signal indicative of said at least one of the FIFO level and the rate of change of the FIFO level; and

a low pass filter coupled and configured generate the feedback signal by low pass filtering the raw feedback signal.

45. The receiver of claim 44, wherein the raw feedback signal is determined by a sequence of feedback bits, and the low pass filter comprises:

an N-bit shift register coupled to receive sequentially the feedback bits;

an N×

1 bit adder coupled to the shift register and configured to periodically add together all of the feedback bits in the shift register to generate sum bits; and

logic circuitry coupled and configured to generate the feedback signal in response to the sum bits.

46. A receiver for use in a system including a serial link and a transmitter configured to transmit data to the receiver over one or more channels of the link, said data including video data and auxiliary data, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and at least some of said data are transmitted at a data rate determined by a transmitter clock frequency, wherein the receiver includes clock generation circuitry for generating an auxiliary data clock for use in receiving the auxiliary data, wherein the auxiliary data clock has a receiver clock frequency, and wherein the auxiliary clock generation circuitry includes:

circuitry for generating a binary value indicative of a ratio B/A, where A is an integer indicative of the transmitter clock frequency and B is an integer indicative of the receiver clock frequency, said circuitry comprising;

a first counter configured to count repeatedly up to a value equal to 2^m and then to reset, in response to a clock having the transmitter clock frequency, where m is an integer; and

a second counter coupled to the first counter and configured to generate a second count value in response to a clock having the receiver clock frequency and to reset when the first counter resets, whereby each maximum value of the second count value is indicative of said ratio B/A.

47. A communication system, including:

a receiver;

a transmitter; and

a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the video data are transmitted at a video data rate and packets of the auxiliary data are transmitted at an auxiliary data rate, wherein the receiver comprises auxiliary clock generation circuitry configured to generate an auxiliary clock having frequency closely matching the auxiliary data rate, and wherein the receiver is configured to transmit the auxiliary clock to the transmitter over a back channel of the link.

48. The system of claim 47, wherein the is a Digital Video Interface link.