High-speed communications transceiver

• US 7,295,623 B2
• Filed: 07/11/2001
• Issued: 11/13/2007
• Est. Priority Date: 07/11/2001
• Status: Expired due to Term

• Current Assignee: Entropic Communications, LLC (SoftBank Group Corp.)
• Original Assignee: Vativ Technologies, Inc. (Maxlinear Incorporated)
• Inventors: Raghavan, Sreen
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): WILLIAMS, LAWRENCE B
• Application Number:
  US09/904,432
• Publication Number:
  US 20030058955A1
• Time in Patent Office: 2,316 Days
• Field of Search: 375/242, 375/260, 375/285, 375/261, 375/265, 375/279, 370/278, 370/464, 370478-535, 370/480, 370532-545, 332/103, 341/59
• US Class Current: 375/265
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems

Abstract

A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels.

Claims

1. A serializer/deserializer communications system, comprising:

a transmitter, the transmitter coupled to receive N parallel bits of data and transmit the N parallel bits of data into K frequency separated channels on a single conducting differential transmission medium, where N and K are integers each greater than one, the N parallel bits being transmitted into the K frequency separated channels of the sterializer/deserializer system synchronously; and

a receiver coupled to receive a sum signal that includes signals from each of the K frequency separated channels from the single conducting differential transmission medium and recover the N parallel bits of data,

wherein the receiver includes K demodulators, each of the K demodulators receiving signals on one of the K frequency separated channels, at least one of the K demodulators including

an analog down converter that converts the signal corresponding to that channel associated with the at least one of the demodulators to a base-band signal in a single step;

an analog-to-digital converter coupled to receive the base-band signal from the analog down converter and generate a digitized base-band signal;

an equalizer circuit coupled to receive the digitized base-band signal and create an equalized symbol; and

a decoder that synchronously retrieves the equalized symbol and retrieves a decoder that receives the equalized symbol and retrieves bits associated with the at least one of the K demodulators associated with the at least one of the K demodulators.

2. The system of claim 1, wherein the transmitter comprises

a bit allocation circuit that receives the N parallel bits of data and creates K subsets of data bits;

K modulators, wherein each of the K modulators encodes one of the K subsets of the N parallel bits of data and creates an output signal modulated at a carrier frequency associated with one of the K frequency separated channels; and

an adder that receives the output signal from each of the K modulators and generates a transmit sum signal for transmission on the single conducting differential transmission medium.

3. The system of claim 2, wherein at least one of the K modulators includes

a data encoder that receives the one of the K subsets of the N parallel bits of data associated with the at least one of the K modulators and outputs an encoded signal;

a symbol mapper coupled to receive the encoded signal and output a symbol; and

an analog up-converter coupled to receive symbols from the symbol mapper and generate the output signal,

wherein the analog up-converter outputs data at the carrier frequency of one of the K frequency separate channels that corresponds with the at least one of the K modulators.

4. The system of claim 3, further including a digital-to-analog converter coupled between the symbol mapper and the analog up-converter.

5. The system of claim 3, wherein the data encoder is a trellis encoder.

6. The system of claim 3, wherein the symbol mapper is a QAM symbol mapper which maps the encoded output signal into a complex symbol that includes an in-phase signal and a quadrature signal.

7. The system of claim 4, further including a digital filter coupled between the symbol mapper and the digital-to-analog converter.

8. The system of claim 4, further including a low-pass analog filter coupled between the digital-to-analog converter and the analog up-converter.

9. The system of claim 6, wherein the analog up-converter generates a first signal by multiplying the in-phase signal of the complex symbol by a sine function of the carrier frequency, generates a second signal by multiplying the out-of-phase signal of the complex symbol by a cosine function of the carrier frequency, and summing the first signal with the second signal to generate the output signal.

10. The system of claim 1, wherein the single conducting differential transmission medium is a copper backplane and the transmitter includes a differential output driver.

11. The system of claim 1, wherein the single conducting differential transmission medium includes an FR4 copper trace and the transmitter includes a differential output driver.

12. The system of claim 2, wherein a subset of bits at a lower carrier frequency contains more bits than a subset of bits associated with a higher carrier frequency.

13. The system of claim 2, wherein each of the K subsets of data bits includes the same number of data bits.

14. The system of claim 2, wherein the receiver further comprises:

a bit parsing circuit that receives each of the K subsets of data bits from the K demodulators and reconstructs the N data bits transmitted by the transmitter.

15. The system of claim 14, wherein the receiver further includes an input buffer coupled between the K demodulators and the single conducting differential transmission medium.

16. The system of claim 15, wherein the input buffer receives a differential receive sum signal that is input to the analog down converter.

17. The system of claim 1, further including an anti-aliasing filter coupled between the analog down-converter and the analog-to-digital converter.

18. The system of claim 1, further including a variable gain amplifier coupled between the down converter and the analog-to-digital converter, the variable gain amplifier being controlled by an automatic gain circuit.

19. The system of claim 1, wherein the digitized base-band signal includes an in-phase signal and a quadrature signal and the analog down-converter multiplies the sum signal by a cosine function to retrieve the in-phase signal and by a sine function to retrieve the quadrature signal.

20. The system of claim 1 further including an adaptively controlled digital filter coupled between the digital-to-analog converter and the equalizer.

21. The system of claim 20, further including a phase-rotator coupled between the adaptively controlled digital filter and the equalizer.

22. The system of claim 1, wherein the equalizer parameters are adaptively chosen.

23. A method of communicating between components over a single conducting differential transmission medium, comprising:

synchronously serializing N bits into K subsets of bits;

encoding each of the K subsets of bits to form encoded subsets of bits;

mapping each of the K encoded subsets of bits onto a symbol set to generate K symbols representing each of the K subsets of bits;

converting each of the K symbols to K analog signals;

up-converting each of the K analog signals in a single analog up-conversion step to form K up-converted signals corresponding with a set of K carrier frequencies;

summing the K up-converted signals representing each of the K subsets of bits to generate a transmit sum signal;

coupling the transmit sum signal to the single conducting differential transmission medium;

receiving a receive sum signal from the single conducting differential transmission medium, the receive sum signal being the transmit sum signal after transmission through the single conducting differential transmission medium;

down-converting the received sum signal in a single analog down-conversion step for each of the K carrier frequencies into a set of K signals at a base band frequency;

digitizing each of the set of K signals to form K digitized signals;

equalizing each of the K digitized signals to receive K equalized symbols; and

decoding each of the K synchronously equalized symbols to reconstruct the K subsets of bits; and

parsing K subsets of bits ; and

parsing K subsets of bits into N deserialized bits.

24. The method of claim 23, wherein symbols transmitted at lower carrier frequencies represent fewer bits than symbols transmitted at higher carrier frequencies.

25. The method of claim 23, wherein encoding each of the K subsets of bits includes encoding at least one of the K subsets of bits with a trellis encoder.

26. The method of claim 23, wherein mapping each of the encoded subsets of bits includes QAM mapping.

27. The method of claim 23, further providing digital filtering prior to converting the K symbols to K analog signals.

28. The method of claim 23, further providing analog filtering of each of the K analog signals.

29. The method of claim 23, wherein receiving the receive sum signal includes receiving a differential signal from a copper backplane.

30. The method of claim 23 further including providing automatic gain conversion for each of the set of K signals prior to digitizing each of the set of K signals.

31. The method of claim 23, further including anti-aliasing filtering prior to analog-to-digital conversion.

32. The method of claim 23 further including providing adaptively controlled filtering for timing recovery.

33. The method of claim 23 wherein the K equalized symbols are complex and further providing adaptively controlled phase rotation.

34. The method of claim 23 wherein decoding the equalized symbols includes trellis decoding and QAM decoding.

35. A transceiver chip for a serializer/deserializer system, comprising:

a transmitter portion, the transmitter portion coupled to receive N parallel bits of data and transmit the N parallel bits of data into a first set of K frequency separated channels on a first single conducting differential transmission medium, the N parallel bits being transmitted into the K frequency separated channels of the serializer-deserializer system synchronously where N and K are integers each greater than one; and

a receiver portion coupled to receive data from a second set of K frequency separated channels from a second single conducting differential transmission medium and recover a second N parallel bits of data, wherein the receiver portion includes,

K demodulators, each of the K demodulators coupled to receive a signal from the second single conducting differential transmission medium, the signal being a transmit sum signal transmitted through the second single conducting differential transmission medium, and retrieving one of the K subsets of data bits and a bit parsing circuit that receives each of the K subsets of data bits from the K demodulators and reconstructs the N data bits transmitted by the transmitter, and

wherein at least one of the K demodulators comprises

an analog down-conversion circuit that receives the signal from the second single conducting differential transmission medium and generates a symbol by converting the signal at the carrier frequency appropriate for the one of the K demodulators,

an analog to digital converter coupled to digitize the symbol from the analog down conversion circuit,

an equalizer circuit coupled to receive the digitized symbol from the analog to digital converter and create an equalized symbol; and

a decoder which receives the equalized symbol and synchronously retrieves the one of the K subsets of bits associated with the at least one of the K demodulators.

36. The chip of claim 35, wherein the first set of K frequency separated channels have substantially identical carrier frequencies with the second set of K frequency separated channels.

37. The chip of claim 35, wherein the transmitter comprises:

a bit allocation circuit that receives the N parallel bits of data and creates K subsets of data bits; and

K modulators, wherein each of the K modulators encodes one of the K subsets of the N parallel bits of data and creates an output signal modulated at a carrier frequency associated with one of the first set of K frequency separated channels; and

an adder that receives the output signal from each of the K modulators and generates a transmit sum signal for transmission on the first single conducting differential transmission medium.

38. The chip of claim 37, wherein at least one of the K modulators includes

a data encoder that receives the one of the K subsets of the N parallel bits of data associated with the at least one of the K modulators and outputs an encoded signal;

a symbol mapper coupled to receive the encoded signal and output a symbol;

a digital to analog converter that digitizes the symbols from the symbol mapper; and

an analog up-converter coupled to receive the digitized symbols from the digital to analog converter and generate the output signal,

wherein the up-converter outputs data at the carrier frequency of one of the K frequency separate channels that corresponds with the at least one of the K modulators.

39. The chip of claim 38, wherein the encoder is a trellis encoder and the symbol mapper is a QAM symbol mapper.