Phase alignment circuitry and methods

• US 7,295,641 B1
• Filed: 11/26/2003
• Issued: 11/13/2007
• Est. Priority Date: 11/26/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wortman, Curt, Berube, Jean Luc
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): GHULAMALI, QUTBUDDIN
• Application Number:
  US10/722,665
• Time in Patent Office: 1,448 Days
• Field of Search: 375/329, 375/330, 375/226, 375/371, 375/362, 375/374, 375/372, 375/355, 375/376, 375/375, 375/365, 370/324, 327/152, 327/141
• US Class Current: 375/371
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling clock signal (derived from the reference clock signal). Information about which amounts of progressively greater phase shift in the sampling clock signal cause loss of alignment between a training pattern and training data in the data signal can be used for such purposes as identifying the amount of phase of shift of the reference clock signal that will be best for use in sampling the data signal during normal (post-training) operation.

Claims

1. A method of detecting phase of transitions in a data signal relative to a reference clock signal comprising:

producing a plurality of phase-shifted versions of the reference clock signal;

using each of the plurality of phase-shifted versions of the reference clock signal in order of magnitude of phase shift to sample the data signal and thereby produce samples of the data signal;

comparing the samples to a training pattern that is initially aligned with training data in the data signal;

re-aligning the training pattern with the training data each time use of one of the plurality of phase-shifted versions of the reference clock signal causes the training pattern to become misaligned with the training data; and

analyzing information including which of the plurality of phase-shifted versions of the reference clock signal caused misalignment to approximate the phase of the transitions.

2. The method defined in claim 1 further comprising:

selecting one of the versions for use in sampling the data signal after the training data based at least in part on the phase of the transitions as approximated in the analyzing.

3. The method defined in claim 2 wherein the data signal has a unit interval corresponding to duration of each bit in the data signal, and wherein the selecting selects one of the versions that is near the center of the unit interval.

4. The method defined in claim 1 wherein each of the plurality of phase-shifted versions is delayed by the same amount of delay relative to an immediately less phase-shifted one of the versions.

5. The method defined in claim 4 wherein the delay is selected so that the unit interval is not an integer multiple of the delay.

6. The method defined in claim 5 wherein the plurality of phase-shift versions of the reference clock signal includes n versions, and wherein n times the delay is greater than two unit intervals.

7. Apparatus for detecting phase of transitions in a data signal relative to a reference clock signal comprising:

a plurality of delay circuit elements for producing a plurality of phase-shifted versions of the reference clock signal;

selection circuitry for selectively selecting each of the plurality of phase-shifted versions of the reference clock signal in order of magnitude of phase shift as a sampling clock signal for sampling the data signal;

comparison circuitry for comparing samples of the data signal, taken using the sampling clock signal, to a training pattern;

alignment circuitry for initially aligning the training pattern with training data in the data signal and for subsequently re-aligning the training pattern with the training data each time use of one of the plurality of phase-shifted versions of the reference clock signal causes the training pattern to become misaligned with the training data; and

circuitry for monitoring which of the plurality of phase-shifted versions of the reference clock signal caused misalignment of the training pattern with the training data.

8. The apparatus defined in claim 7 wherein the delay circuit elements are connected in series and all have the same amount of delay.

9. The apparatus defined in claim 8 wherein the amount of delay is selected so that the unit interval is not an integer multiple of the amount of delay.

10. The apparatus defined in claim 9 wherein the plurality of phase-shifted versions of the reference clock signal includes n versions, and wherein n times the amount of delay is greater than two unit intervals.

11. The apparatus defined in claim 7 wherein the alignment circuitry comprises:

means for selectively recirculating the training pattern in synchronism with the sampling clock signal.

12. The apparatus defined in claim 7 wherein the circuitry for monitoring comprises:

means for determining the approximate phase of the data signal relative to the reference clock signal based at least in part on which of the versions cause the misalignment.

13. The apparatus defined in claim 7 further comprising:

means for selecting one of the versions for use in producing a retimed version of the data signal.

14. A programmable logic device including apparatus as defined in claim 7.

15. A digital processing system comprising:

a processing circuitry;

a memory coupled to the processing circuitry; and

a programmable logic device as claimed in claim 14 coupled to the processing circuitry and the memory.

16. A printed circuit board on which is mounted a programmable logic device as claimed in claim 14.

17. The printed circuit board as claimed in claim 16 further comprising:

a memory mounted on the printed circuit board and coupled to the programmable logic device.

18. The printed circuit board as claimed in claim 16 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.

19. Apparatus for detecting phase of transitions in a data signal relative to a reference clock signal comprising:

a plurality of delay circuit elements for producing a plurality of phase-shifted versions of the reference clock signal;

selection circuitry for selectively selecting each of the phase-shifted versions of the reference clock signal in order of magnitude of phase shift as a sampling clock signal for sampling the data signal;

comparison circuitry for comparing samples of the data signal, taken using the sampling clock signal, to a training pattern;

alignment circuitry for initially aligning the training pattern with training data in the data signal and for subsequently re-aligning the training pattern with the training data each time use of one of the phase-shifted versions of the reference clock signal causes the training pattern to become misaligned with the training data; and

circuitry for monitoring which of the phase-shifted versions of the reference clock signal caused misalignment of the training pattern with the training data, wherein the selection circuitry includes means for advancing to a next one of the phase-shifted versions of the reference clock signal after the comparison circuitry detects an instance of data corresponding to the training pattern in the data signal or a non-correspondence between the data signal and the training pattern.

20. Apparatus for detecting phase of transitions in a data signal relative to a reference clock signal comprising:

a plurality of delay circuit elements for producing a plurality of phase-shifted versions of the reference clock signal;

selection circuitry for selectively selecting each of the phase-shifted versions of the reference clock signal in order of magnitude of phase shift as a sampling clock signal for sampling the data signal;

comparison circuitry for comparing samples of the data signal, taken using the sampling clock signal, to a training pattern;

alignment circuitry for initially aligning the training pattern with training data in the data signal and for subsequently re-aligning the training pattern with the training data each time use of one of the phase-shifted versions of the reference clock signal causes the training pattern to become misaligned with the training data; and

circuitry for monitoring which of the phase-shifted versions of the reference clock signal caused misalignment of the training pattern with the training data, wherein the alignment circuitry comprises;

means for selectively recirculating the training pattern in synchronism with the sampling clock signal and wherein the means for selectively recirculating comprises;

means for halting the recirculating during initial aligning and subsequent re-aligning of the training pattern with the training data.

21. A method of determining an amount of phase shift of a reference clock signal that will render that signal advantageous for use in sampling a data signal that may be skewed relative to the reference clock signal comprising:

aligning a training pattern with training data in the data signal;

using a sampling clock signal based on the reference clock signal to sample the data signal and advance the training pattern;

comparing the advancing training pattern to the data signal samples until the training pattern is complete or until a lack of correspondence between the training pattern and a data signal sample is detected;

shifting the phase of the sampling clock signal by a predetermined amount after completion of the comparing;

re-aligning the training pattern with the training data if the comparing is completed by detection of a lack of correspondence;

repeating the using, comparing, shifting, and re-aligning until the total amount of phase shift due to the shifting is at least greater than the duration of any two successive bits in the data signal; and

sampling the data signal subsequent to the training data with a phase that is determined based at least in part on information as to which iterations of the comparing were completed by detection of a lack of correspondence.