Constant gain digital predistortion controller for linearization of non-linear amplifiers

• US 7,295,815 B1
• Filed: 03/29/2006
• Issued: 11/13/2007
• Est. Priority Date: 11/21/2001
• Status: Expired due to Term

• Current Assignee: Maxlinear Asia Singapore Pte Ltd. (Maxlinear Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Wright, Andrew S., Ho, Derek J. W., Klijsen, Bartholomeus T. W.
• Primary Examiner(s): Nguyen; Simon
• Application Number:
  US11/392,460
• Time in Patent Office: 594 Days
• Field of Search: 455/114.2, 455/114.3, 455/126, 455/127.1, 455/127.2, 375296-297, 330/149
• US Class Current: 455/91
• CPC Class Codes: H01Q 1/243 with built-in antennas
• CPC Class Codes: H01Q 3/2605 Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays
• CPC Class Codes: H01Q 3/2682 Time delay steered arrays
• CPC Class Codes: H03F 1/3223 using feed-forward H03F1/3211 takes precedence
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3294 Acting on the real and imaginary components of the input signal
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 2200/447 the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/468 the temperature being sensed
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion
• CPC Class Codes: H04B 2001/0433 with linearisation using feedback
• CPC Class Codes: H04B 2001/0441 with linearisation using feed-forward

Abstract

The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques. Embodiments of the invention can automatically adjust the characteristics of a predistorted signal so that a deviation from overall linearity is compensated and subsequently reduced while maintaining a nearly constant gain attribute.

Claims

1. A normalizing signal pre-processor that receives a reference signal and an observed signal as inputs and generates a modified observed signal as an output, the normalizing signal pre-processor comprising:

a first multiplier circuit adapted to scale the observed signal;

a subtraction circuit adapted to generate an error signal from a difference between the modified observed signal and the reference signal; and

adaptation logic adapted to receive the reference signal, the observed signal, the modified signal, and the error signal as inputs, and to adaptively adjust the scaling by the first multiplier circuit to reduce the magnitude of the error signal.

2. The normalizing signal pre-processor as defined in claim 1, further comprising:

a second multiplier circuit configured multiply a data stream associated with the observed signal with a signal with a frequency;

a digitally numerically controlled oscillator that provides the signal with the frequency, where the digitally numerically controlled oscillator is responsive to a control word from adaptation logic, where the control word sets the frequency of the signal; and

where the adaptation logic is configured to adaptively adjust the control word to the digitally numerically controlled oscillator to reduce a frequency offset present in the error signal.

3. The normalizing signal pre-processor as defined in claim 1, further comprising a second multiplier circuit configured to adjust a phase of a data stream associated with the observed signal in response to a phase adjust signal from the adaptation logic, where the phase adjust signal reduces the magnitude of the error signal.

4. The normalizing signal pre-processor as defined in claim 1, further comprising an interpolating finite impulse response filter configured to provide oversamples of a data stream associated with the observed signal in fractions of a sample period, where the interpolating finite impulse response filter is further configured to permit the adaptation logic to selectively delay the data stream through the interpolating finite impulse response filter to reduce a misalignment of time in the error signal.

5. The normalizing signal pre-processor as defined in claim 1, further comprising:

a second multiplier circuit configured multiply a data stream associated with the reference signal with a signal with a frequency;

a digitally numerically controlled oscillator that provides the signal with the frequency, where the digitally numerically controlled oscillator is responsive to a control word from adaptation logic, where the control word sets the frequency of the signal; and

where the adaptation logic is configured to adaptively adjust the control word to the digitally numerically controlled oscillator to reduce a frequency offset present in the error signal.

6. The normalizing signal pre-processor as defined in claim 1, further comprising a second multiplier circuit configured to adjust a phase of a data stream associated with the reference signal in response to a phase adjust signal from the adaptation logic, where the phase adjust signal reduces the magnitude of the error signal.

7. The normalizing signal pre-processor as defined in claim 1, further comprising an interpolating finite impulse response filter configured to provide oversamples of a data stream associated with the reference signal in fractions of a sample period, where the interpolating finite impulse response filter is further configured to permit the adaptation logic to selectively delay the data stream through the interpolating finite impulse response filter to reduce a misalignment of time in the error signal.

8. The normalizing signal pre-processor as defined in claim 1, further comprising a second subtraction circuit adapted to receive a DC adjust signal from the adaptation logic, where the adaptation logic is further configured to adaptively adjust the DC offset to reduce a DC offset in the error signal.

9. The normalizing signal pre-processor as defined in claim 1, further comprising at least one additional signal processing circuit disposed in a signal path between the first multiplier circuit and the subtraction circuit, where the additional signal processing circuit includes at least one signal processing circuit selected from the group consisting of a frequency offset circuit, a phase adjustment circuit, a delay adjustment circuit, and a DC adjustment circuit.

10. An RF power amplifier system that embodies the normalizing signal pre-processor of claim 1.

11. A cellular base station that embodies the normalizing signal pre-processor of claim 1.