Centerplaneless computer system

• US 7,296,106 B2
• Filed: 06/28/2002
• Issued: 11/13/2007
• Est. Priority Date: 06/28/2002
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Cypher, Robert E., Doblar, Drew G.
• Primary Examiner(s): Rinehart; Mark H.
• Assistant Examiner(s): Cleary; Thomas J
• Application Number:
  US10/184,474
• Publication Number:
  US 20040003158A1
• Time in Patent Office: 1,964 Days
• Field of Search: 710 3- 4, 710/38, 710300-304, 710316-317, 710/305, 710/11, 709/218, 439/65, 712/11, 711/5, 711/115, 714 1- 3, 714/747, 714/800, 714/43, 714/52, 714/820
• US Class Current: 710/302
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A computer system which may allow a centerplaneless design. The computer system may include various client circuit boards including processor circuit boards, memory circuit boards and switch circuit boards. The processor circuit boards may each include at least one processor, while the memory circuit boards may each include memory which is accessible by each processor. The switch circuit boards may include a plurality of detachable connectors for interconnecting each of the processor circuit boards to each of the memory circuit boards. At least one of the switch circuit boards may convey redundant memory access information. Each of the boards may be hot swappable.

Claims

1. A computer system comprising:

a plurality of processor circuit boards each including at least one processor;

a plurality of memory circuit boards each including memory accessible by each of said at least one processor of each of said plurality of processor circuit boards; and

a plurality of switch circuit boards each including a plurality of detachable connectors for directly mating each of said plurality of switch circuit boards to each of said plurality of processor circuit boards and to each of said plurality of memory circuit boards, wherein each switch circuit board of said plurality of switch circuit boards conveys a respective portion of memory access information; and

at least one additional switch circuit board that is separate from said plurality of switch circuit boards, wherein said additional switch circuit board is coupled between said plurality of processor circuit boards and said plurality of memory circuit boards, and configured to, during operation, convey only redundant memory access information that is based upon the respective portion of memory access information conveyed by each of said plurality of switch circuit boards, such that, in response to removal of any one of said plurality of switch circuit boards said respective portion of memory access information conveyed by said removed switch circuit board is logically reconstructed, using an exclusive-OR function, from said redundant memory access information and remaining respective portions of memory access information.

2. The computer system as recited in claim 1, wherein any one of said plurality of processor circuit boards is hot swappable.

3. The computer system as recited in claim 1, wherein any one of said plurality of switch circuit boards is hot swappable.

4. The computer system as recited in claim 1, wherein any one of said plurality of memory circuit boards is hot swappable.

5. The computer system as recited in claim 1 further comprising a plurality of input/output circuit boards each including an input/output bridge and coupled to access said memory via said plurality of switch circuit boards.

6. The computer system as recited in claim 5, wherein each of said input/output circuit boards is hot swappable.

7. The computer system as recited in claim 1, wherein each of said plurality of switch circuit boards includes address switch circuits configured to route address information.

8. The computer system as recited in claim 7, wherein said address information is conveyed in slices across at least two of said plurality of switch circuit boards.

9. The computer system as recited in claim 8, wherein said redundant memory access information includes redundant address information.

10. The computer system as recited in claim 9, wherein said redundant address information is conveyed across said at least one additional switch circuit board.

11. The computer system as recited in claim 10, wherein said redundant address information represents parity for said slices.

12. The computer system as recited in claim 1, wherein each of said plurality of switching circuit boards includes data switch circuits configured to route data.

13. The computer system as recited in claim 12, wherein said data is conveyed in slices across at least two of said plurality of switch circuit boards.

14. The computer system as recited in claim 13, wherein said redundant memory access information includes redundant data information.

15. The computer system as recited in claim 14, wherein redundant data information is conveyed across said at least one additional switch circuit board.

16. The computer system as recited in claim 15, wherein said redundant data information represents parity for said slices.

17. The computer system as recited in claim 1 further comprising a first plurality of fans and a second plurality of fans, wherein said first and said second plurality of fans are configured to independently provide cooling air for said plurality of processor circuit boards, said plurality of switch circuit boards and said plurality of memory circuit boards.

18. The computer system as recited in claim 17, wherein each of said first plurality of fans and each of said second plurality of fans is hot swappable.

19. The computer system as recited in claim 1 further comprising a first power distribution board and a second power distribution board coupled to independently distribute power to each of said plurality of processor circuit boards and each of said plurality of memory circuit boards.

20. The computer system as recited in claim 19, wherein said first power distribution board and said second power distribution board are each hot swappable.

21. A method comprising:

providing a plurality of processor circuit boards each including at least one processor;

providing a plurality of memory circuit boards each including memory accessible by each of said at least one processor of each of said plurality of processor circuit boards;

providing a plurality of switch circuit boards each including a plurality of detachable connectors;

detachably mating each of said plurality of processor circuit boards and each of said plurality of memory circuit boards directly to each of said plurality of switch circuit boards via said plurality of detachable connectors;

conveying a respective portion of memory access information on each of said plurality of switch circuit boards; and

during operation, conveying only redundant memory access information on at least one additional switch circuit board that is separate from said plurality of switch circuit boards, such that, in response to removal of any one of said plurality of switch circuit boards said respective portion of memory access information conveyed by said removed switch circuit board is logically reconstructed, using an exclusive-OR function, from said redundant memory access information and remaining respective portions of memory access information;

wherein said redundant memory access information is based upon the respective portion of memory access information conveyed by each of said plurality of switch circuit boards.

22. A computer system comprising:

a plurality of processor circuit boards each including at least one processor;

a plurality of memory circuit boards each including memory accessible by each of said at least one processor of each of said plurality of processor circuit boards; and

a plurality of switch circuit boards including a plurality of detachable connectors for directly mating each of said plurality of switch circuit boards to each of said plurality of processor circuit boards and to each of said plurality of memory circuit boards;

wherein a selected memory location is accessible by conveying memory access information from the at least one processor through the plurality of switch circuit boards to at least one of said plurality of memory circuit boards, wherein each switch circuit board of said plurality of switch circuit boards conveys a respective portion of said memory access information; and

at least one additional switch circuit board that is separate from said plurality of switch circuit boards, and configured to, during operation, convey from the at least one processor to at least one of said plurality of memory circuit boards, only redundant memory access information that is based upon the respective portion of memory access information conveyed by each of said plurality of switch circuit boards such that, in the event one of the plurality of switch circuit boards is removed, said memory access information conveyed by the removed switch circuit board is logically reconstructed, using an exclusive-OR function, from the respective portions of said memory access information conveyed by each remaining switch circuit board of said plurality of switch circuit boards and the redundant memory access information.

23. The computer system as recited in claim 22, wherein any one of said plurality of processor circuit boards, any one of said plurality of switch circuit boards, and any one of said plurality of memory circuit boards is hot swappable.

24. The computer system as recited in claim 22 further comprising a plurality of input/output circuit boards each including an input/output bridge and coupled to access said memory via said plurality of switch circuit boards.

25. The computer system as recited in claim 24, wherein each of said input/output circuit boards is hot swappable.

26. The computer system as recited in claim 22, wherein each of said plurality of switch circuit boards includes address switch circuits and data switch circuits configured to route address information and data information, respectively.

27. The computer system as recited in claim 26, wherein said address information and said data information is conveyed in slices across at least two of said plurality of switch circuit boards.

28. The computer system as recited in claim 27, wherein said redundant memory access information includes redundant address information and redundant data information.

29. The computer system as recited in claim 28, wherein said redundant address information and said redundant data information is conveyed across said at least one additional switch circuit board.

30. The computer system as recited in claim 29, wherein said redundant address information and said redundant data information represents parity for said slices.