High bandwidth memory management using multi-bank DRAM devices

• US 7,296,112 B1
• Filed: 12/10/2003
• Issued: 11/13/2007
• Est. Priority Date: 12/10/2002
• Status: Expired due to Fees

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Greenfield Networks, Inc. (Cisco Systems, Inc.)
• Inventors: Devanagondi, Harish R., Yarlagadda, Ramesh, Desai, Shwetal
• Primary Examiner(s): Choi; Woo H.
• Application Number:
  US10/734,082
• Time in Patent Office: 1,434 Days
• Field of Search: 711/105, 711/157
• US Class Current: 711/105
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence

Abstract

The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are stored in the plurality of banks in accordance with an access scheme that hides pre-charging of rows behind data transfers. A storage distribution control module is communicatively coupled to a memory comprising a plurality of storage request queues, and a retrieval control module is communicatively coupled to a memory comprising a plurality of retrieval request queues. In one example, each request queue may be implemented as a first-in-first-out (FIFO) memory buffer. The plurality of storage request queues are subdivided into sets as are the plurality of retrieval queues. Each is set is associated with a respective DRAM device. A scheduler for each respective DRAM device schedules data transfer between its respective storage queue set and the DRAM device and between its retrieval queue set and the DRAM device independently of the scheduling of the other devices, but based on a shared criteria for queue service.

Claims

1. A method for accessing a plurality of dynamic random access:

memory (DRAM) devices in parallel, each DRAM device having at least one memory bank, the method comprising;

for each storage request for a data word, determining a distribution of data segments of the data word in a plurality of memory banks based on the usage of the memory banks, the plurality of memory banks being among the memory banks of the plurality of DRAM devices, wherein a first data segment of a first data word and a second data segment of a second data word are distributed to a same memory bank according to a distribution of data segments of the first and second data words;

determining a sequence of retrieving the data segments of the first and second data words, the sequence of retrieving the first data segment and the second data segment determined by retrieval of other data segments from the same memory bank;

retrieving the data segments of the first and second data words in parallel from the plurality of memory banks based on the distribution of the data segments of the first and second data words and the sequence; and

reassembling the retrieved data segments into the first and second data words.

2. The method of claim 1 further comprising:

receiving a retrieval request for the first data word and a retrieval request for the second data word, wherein the sequence of retrieving the first data segment and the second data segment can be different from the order of the retrieval requests received.

3. The method of claim 1 wherein at least one of the first and second data words has a maximum word size.

4. The method of claim 1 wherein at least one of the first and second data words includes a cell of a packet.

5. The method of claim 1 wherein at least one of the first and second data words has a fixed word size.

6. The method of claim 1 wherein at least one of the first and second data words has a variable word size.

7. The method of claim 1, further comprising:

partitioning the first and second data words into the data segments; and

storing the data segments in parallel into the plurality of memory banks based on the distribution.

8. The method of claim 7, wherein storing the data segments in parallel into the plurality of memory banks based on the distribution comprises:

determining an in-bank burst length based upon a maximum word size, a total number of the plurality of memory banks, and a data width of an individual memory bank; and

storing the data segments in parallel into the plurality of memory banks based on the distribution in a burst having the in-bank burst length.

9. The method of claim 1 wherein data segments of at least one of the first and second data words are stored in at least one memory bank from each of the plurality of DRAM devices.

10. The method of claim 1, wherein the sequence of retrieving the data segments within a first DRAM device is independent from the sequence of retrieving the data segments within a second DRAM device, the first and second DRAM devices being among the plurality of DRAM devices, the method further comprising:

scheduling the storing of the data segments independently within a DRAM device.

11. The method of claim 1 wherein retrieving the data segments in parallel comprises:

determining a starting memory bank in each of the plurality of DRAM devices storing at least one of the data segments; and

retrieving the data segments in parallel from the starting memory banks.

12. The method of claim 1, wherein the data segments stored in the same memory bank are retrieved in one burst.

13. A system for providing fast access to dynamic random access memory (DRAM) devices, the system comprising:

a plurality of DRAM devices, each DRAM device having at least one memory bank;

a processor; and

a memory unit comprising a computer usable medium that comprises microcode for execution by the processor to cause the processor to perform the operations of;

for each storage request for a data word, determining a distribution of data segments of a data word in a plurality of memory banks based on the usage of the memory banks, the plurality of memory banks being among the memory banks of the plurality of DRAM devices, wherein a first data segment of a first data word and a second data segment of a second data word are distributed to a same memory bank according to a distribution of data segments of the first and second data words;

determining a sequence of retrieving the data segments of the first and second data words, the sequence of retrieving the first data segment and the second data segment determined by retrieval of other data segments from the same memory bank;

retrieving the data segments of the first and second data words in parallel from the plurality of memory banks based on the distribution of the data segments of the first and second data words and the sequence; and

reassembling the retrieved data segments into the first and second data words.

14. The system of claim 13, wherein the computer usable medium further comprises microcode for execution by the processor to cause the processor to perform the operation of:

partitioning the first and second data words into the data segments; and

storing the data segments in parallel into the plurality of memory banks based on the distribution.

15. A system for providing fast access to dynamic random access memory (DRAM) devices, the system comprising:

a plurality of DRAM devices, each DRAM device having at least one memory bank;

a storage distribution control module configured to partition a first data word and a second data word into data segments, to determine a distribution of data segments of a data word in a plurality of memory banks based on the usage of the memory banks responsive to each storage request for the data word, the plurality of memory banks being among the memory banks of the plurality of DRAM devices, wherein a first data segment of the first data word and a second data segment of the second data word are distributed to a same memory bank according to a distribution of data segments of the first and second data words;

a scheduler associated with each DRAM device, configured to determine a storage schedule to store the data segments of the first and second data words distributed to the associated DRAM device in the plurality of memory banks, and to determine a retrieval schedule to retrieve the data segments of the first and second data words stored in the associated DRAM device from the plurality of memory banks, the retrieval schedule of retrieving the first data segment and the second data segment determined by retrieval of other data segments from the same memory bank, the storage schedule and the retrieval schedule of one DRAM device being independent of the storage schedules and retrieval schedules of other DRAM devices; and

a retrieval control module configured to retrieve the data segments in parallel from the plurality of memory banks based on the distribution and the retrieval schedule, and to reassemble the retrieved data segments into the first and second data words.