Method to locate logic errors and defects in digital circuits

• US 7,296,201 B2
• Filed: 10/29/2005
• Issued: 11/13/2007
• Est. Priority Date: 10/29/2005
• Status: Active Grant

• Current Assignee: DAFCA, Inc. (Ceallaigh Group LLC)
• Original Assignee: DAFCA, Inc. (Ceallaigh Group LLC)
• Inventors: Abramovici, Miron
• Primary Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US11/262,084
• Publication Number:
  US 20070101216A1
• Time in Patent Office: 745 Days
• Field of Search: 714/724, 714/726
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence

Abstract

When, in the course of an integrated circuit'"'"'s functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

Claims

1. A method for testing a circuit when in the course of said testing information is developed that indicates that an error is present in one or more signals S_j,l(k), where j is an index that distinguishes different ones of said signals, l is a level indicator that is initially set at 0, and k indicates a number of operational clock periods following a given condition when said error signals appear, said method starting with a variable m equal to k, and comprising the steps of:

for at least one of the signals S_j,i(m),

(a) identifying an associated fanin cone;

(b) re-testing said circuit, and capturing input signals of said fanin cone;

(c) processing information about said fanin cone to

(1) identify an error within said fanin cone, or

(2) identify a collection of input signals of said fanin code that potentially are at in error, and further identify said collection of input signals to be

(i) input signals of the circuit, or

(ii) internal signals of said circuit S_j,i(k), with index l incremented by 1, that are output signal of memory elements of said circuit, each storing associated p logic values, and each having been subjected to an input signal S_j,i(m−

p);

(d) setting m to m−

p, thus forming signals S_j,i(m), and with respect to each of the formed signals S_j,l(m) returning to step (a); and

(e) terminating said method when no input signals of any fanin code is identified as an output signal of a memory element of said circuit.

2. The method of claim 1 where said steps (b) and (c) are carried out for all of said signals S_j,l(m).

3. The method of claim 2 where said step of terminating also terminates when the value of m−

p for setting to m in step (d) is less than 1.

4. The method of claim 1 where p=1.

5. The method of claim 1 where said error that is present k operational clock periods following occurrence of said given condition is observable at clock k+1.

6. The method of claim 1 further comprising a step of examining said circuit to identify the value of k.

7. The method of claim 1 where said testing of the circuit is executed in a system that includes said circuit connected to other circuits.

8. The method of claim 7 where said testing constitutes an at speed functional test of said system.

9. The method of claim 1 where said step of terminating execution of said method also terminates when step (c) identifies an error within said fanin cone.

10. The method of claim 1 including step that, when step (c) identifies an error within said fanin cone, performs a focused test on said fanin cone to identify cause of said error.

11. The method of claim 1 where said circuit is an integrated circuit and said signals S_j(k) are outputs of assertion-checking circuits that are either embedded in the integrated circuit or configured in a configurable portion of said integrated circuit.

12. The method of claim 11 where said configurable portion is in a wrapper associated with a block of said integrated circuit.

13. The method of claim 1 where said circuit is an integrated circuit and said signals S_j(k) are outputs that are known to be erroneous through comparison with expected results.

14. The method of claim 1, executed for each of said signals S_j(m).

15. The method of claim 14 where said processing is carried out for the respective fanin cones associated with all of the signals S_j(m) effectively concurrently.

16. The method of claim 14 where said processing is carried out for the respective fanin cones associated with all of the signals S_j(m) substantially sequentially.

17. The method of claim 1 where said step of processing comprises

(i) simulating internal signals of the fanin cone, based on said input signals captured in step (b), and developing a simulated output signal of said fanin cone;

(ii) determining whether said simulated output signal matches said signal S_j(m);

(iii) when said step (ii) of said step of processing determines that said simulated output signal of said fanin cone does not match S_j(m), concluding that said fanin cone is faulty; and

(iv) when said step (ii) of said step of processing determines that the simulated output signal matches said S_j(m), concluding that the fanin cone operates properly, and extending one or more error paths from the output signal of the fanin cone toward the input signals of said fanin cone to identify thereby said collection of input signals.

18. The method of claim 17 where said extending said one or more error paths comprises steps of comparing the simulated internal signals of the fanin cone to signals developed for said fanin cone by use of a line justification algorithm that assumes an output signal of said fanin cone to be S_j(m).

19. The method of claim 1 where said capturing of input signals in step (b) is involves a scan-out operation.

20. A method for testing a circuit comprising the steps of:

at-speed testing of the circuit with a sequence of input signals;

stopping said at-speed testing when an error signal S_j,l(k) is detected, where the index j distinguished different signals, subscript l designates a level, which at this step is 0, and k is a number of at-speed operational clock periods following a given condition when said error signal is detected; and

starting with variable m=k, and setting signal S_j,l(m) as a subject signal, executing an error localization process that

(a) identifies an associated fanin cone of the subject signal, and input signals of said associated fanin cone;

(b) re-tests said circuit by once applying said sequence of input signals, and capturing said input signals of the fanin cone at clock period m following said given condition;

(c) from information regarding design of said circuit, and logic value of the subject signal, computes logic values of said input signals of said associated fanin cone, and analyzes the computed logic values to

(1) identify an error within said fanin cone, or

(2) identify a collection input signals of said fanin code that potentially are at in error, and further identify said collection of input signals to be

(i) input signals of the circuit, or

(ii) internal signals of said circuit, S_j,l(k), with index l incremented by 1, that are output signals of flip-flops of said circuit that have been respectively subjected to input signal S_j,l(m−

1);

(d) decrements m by 1, thus forming signal to S_j,l(m) as a new subject signals, and with respect to each of the formed signals S_j,l(m) returns to step (a); and

(e) terminating said method when no input signals of any fanin code is identified as an output signal of a flip-flop of said circuit.