Error correction cache for flash memory

• US 7,296,213 B2
• Filed: 12/11/2002
• Issued: 11/13/2007
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kiris, Cahide, Vainsencher, Leonardo
• Primary Examiner(s): CHASE, SHELLY A
• Application Number:
  US10/316,401
• Publication Number:
  US 20040117686A1
• Time in Patent Office: 1,798 Days
• Field of Search: 714/784, 714/785
• US Class Current: 714/784
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Claims

1. A system to detect and correct errors in a flash memory, comprising:

an error detection circuit coupled to the flash memory, the error detecting circuit determining if an error occurs in accessing data from a physical block number (PBN) from the flash memory; and

an error correction cache coupled to the error detection circuit, the cache storing one or more PBN entries related to one or more past data accesses and error correction information associated with the one or more PBN entries, the one or more PBN entries being used to determine whether a current data access involves substantially similar data as a past data access, wherein upon detecting an error and if the current data access involves substantially similar data as a past data access, error correction information associated with a PBN entry is applied to correct the error.

2. The system of claim 1, wherein the error correction information includes a corrected page of information or information used to correct the error.

3. The system of claim 1, wherein the error detection circuit generates a syndrome and the error correction information stored in the error correction cache includes a previously determined syndrome.

4. The system of claim 3, wherein the syndrome from the error detection circuit is compared with the previously determined syndrome and if the syndromes match, the error is corrected using the previously determined syndrome and otherwise the error correction information is updated with the syndrome generated by the error detection circuit.

5. The system of claim 1, wherein the error detecting circuit further comprises at least three error detection circuits corresponding to three selectable error detection modes, the error detection circuits being adapted to detect an error based on a selected mode of error detection and correction.

6. The system of claim 5, wherein the flash memory comprises an extra storage area and wherein the three modes of error detection and correction further comprises a first mode to correct one error, a second mode to correct two errors including errors in the extra storage area, and a third mode to correct three errors including errors in the extra storage area.

7. The system of claim 6, wherein the first mode protects against any one symbol error.

8. The system of claim 7, wherein the second mode protects against any two symbol errors, including those in the extra storage area.

9. The system of claim 8, wherein the third mode protects against any three symbol errors, including those in the extra storage area.

10. The system of claim 9, wherein the first mode comprises a Smart Media compatible mode, the second mode further comprises a Reed-Solomon 52 (RS-52) mode, and the third mode further comprises an RS-73 mode.

11. A method to detect and correct errors in a flash memory using an error correction cache, the method comprising:

storing in the error correction cache one or more PBN entries related to one or more past data accesses;

storing error correction information associated with the one or more PBN entries in the error correction cache;

accessing data from a physical block number (PBN) of the flash memory;

determining whether a current data access involves substantially similar data as a past data access using the one or more PBN entries; and

upon detecting an error and if the current data access involves substantially similar data as a past data access, applying error correction information stored in the cache and associated with a PBN entry to correct the data error.

12. The method of claim 11, further comprising:

detecting in hardware an error based on one of three selectable mode of error detection and correction; and

correcting the error by executing error correction software corresponding to the selected mode of error detection and correction.

13. The method of claim 12, wherein the flash memory comprises an extra storage area and wherein the three modes of error detection and correction further comprises a first mode to correct one error, a second mode to correct two errors including errors in the extra storage area, and a third mode to correct three errors including errors in the extra storage area.

14. The method of claim 13, wherein the first mode protects against any one symbol error, the second mode protects against any two symbol errors, including those in the extra storage area, and the third mode protects against any three symbol errors, including those in the extra storage area.

15. The method of claim 13, wherein the first mode comprises a Smart Media compatible mode, the second mode further comprises a Reed-Solomon 52 (RS-52) mode, and the third mode further comprises an RS-73 mode.

16. The method of claim 11, wherein the error correction information includes a corrected page of information or information used to correct the error.

17. The method of claim 11, further comprising generating a syndrome for the data from the accessed PBN, wherein the error correction information stored in the error correction cache includes a previously determined syndrome.

18. The method of claim 17, further comprising comparing the generated syndrome the previously determined syndrome and if the syndromes match, correcting the error using the previously determined syndrome and otherwise updating the error correction information with the generated syndrome.

19. A system to detect and correct errors in a flash memory, comprising:

a processor coupled to the flash memory, the processor adapted to access data from a physical block number (PBN) from the flash memory;

an error detection circuit coupled to the flash memory and the processor, the error detecting circuit notifying the processor if an error occurs in the accessed PBN; and

an error correction cache coupled to the processor, the cache storing one or more PBN entries related to one or more past data accesses and error correction information associated with the one or more PBN entries, the processor using the one or more PBN entries to determine whether a current data access involves substantially similar data as a past data access, wherein upon detecting an error and if the current data access involves substantially similar data as a past data access, the processor applying error correction information associated with a PBN entry to correct the error.

20. The system of claim 19, wherein the error correction information include a corrected page of information or information used to correct the error.

21. The system of claim 19, wherein the error detection circuit generates a syndrome and the error correction information stored in the error correction cache includes a previously determined syndrome.

22. The system of claim 21, wherein the syndrome from the error detection circuit is compared with the previously determined syndrome and if the syndromes match, the error is corrected using the previously determined syndrome and otherwise the error correction information is updated with the syndrome generated by the error detection circuit.