Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions

• US 7,297,582 B2
• Filed: 11/18/2004
• Issued: 11/20/2007
• Est. Priority Date: 05/06/2003
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Abadeer, Wagdi W., Tonti, William R., Rankin, Jed H., Gauthier, Robert J. Jr., Brown, Jeffrey S.
• Primary Examiner(s): Pham; Thanhha S.
• Application Number:
  US10/991,936
• Publication Number:
  US 20050090049A1
• Time in Patent Office: 1,097 Days
• Field of Search: 438/197, 438/221, 438230-231, 438/424, 438/524
• US Class Current: 438/197
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

Claims

1. A method of manufacturing a transistor comprising:

forming a trench in a substrate;

forming spacers in said trench;

after forming said spacers, implanting a drain extension through said trench into said substrate;

filling said trench with a shallow trench isolation (STI) material;

defining a channel region in said substrate on one side said STI material;

forming a source region in said substrate on an opposite side of said channel region from said STI material;

forming a drain region in said substrate on an opposite side of said STI material from said channel region; and

forming a gate above said channel region.

2. The method in claim 1, wherein said spacers control a size of said drain extension.

3. The method in claim 1, wherein said forming of said gate extends a portion of said gate over said STI material.

4. The method in claim 1, wherein said drain extension provides a conductive path between said drain region and said channel region around a lower perimeter of said STI.

5. The method in claim 1, wherein said process of forming said drain region positions said drain region further from said gate than said source region.

6. The method in claim 1 wherein said process of implanting said drain extension comprises protecting regions other than said trench to limit said implanting process to said trench.

7. A method of manufacturing a transistor comprising:

forming a trench in a substrate;

partially filling said trench with a sacrificial material;

forming spacers in said trench above said sacrificial material;

removing said sacrificial material;

implanting a drain extension through said trench into exposed portions of said substrate, wherein said drain extension is implanted to regions of said substrate along sides and a bottom of said trench;

filling said trench with a shallow trench isolation (STI) material;

defining a channel region in said substrate on one side said STI material;

forming a source region in said substrate on an opposite side of said channel region from said STI material;

forming a drain region in said substrate on an opposite side of said STI material from said channel region; and

forming a gate above said channel region.

8. The method in claim 7, wherein said implanting process comprises a vertical implant to form said drain extension in said portion of said substrate along said bottom of said substrate and an angled implant to form said drain extension in said portion of said substrate along said sides of said substrate.

9. The method in claim 7, wherein said spacers and said sacrificial material control the size and location of said drain extension.

10. The method in claim 7, wherein said implanting process forms portions of said drain extensions along sides of said STI from said bottom of said STI to a position partially up said sides of said STI.

11. The method in claim 7, wherein said forming of said gate extends a portion of said gate over said STI material.

12. The method in claim 7, wherein said drain extension provides a conductive path between said drain region and said channel region around a lower perimeter of said STI.

13. The method in claim 7, wherein said process of forming said drain region positions said drain region further from said gate than said source region.

14. The method in claim 7, wherein said process of implanting said drain extension comprises protecting regions other than said trench to limit said implanting process to said trench.