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Composite gate structure in an integrated circuit

  • US 7,297,587 B2
  • Filed: 01/03/2007
  • Issued: 11/20/2007
  • Est. Priority Date: 06/22/2005
  • Status: Expired due to Fees
First Claim
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1. A method of forming an integrated circuit, the method comprising:

  • providing a substrate having a first region and a second region, wherein the first region further comprises a third region and a fourth region;

    forming a high-k dielectric layer on the substrate in the first region;

    forming a first metal layer having a first work function over the high-k dielectric layer in the fourth region;

    forming a second metal layer having a second work function over the high-k dielectric layer in the third region;

    forming a gate dielectric layer over the substrate in the second region;

    forming a silicon layer directly on the second metal layer and the gate dielectric layer;

    patterning the high-k dielectric layer, the second metal layer, and the silicon layer to form a first gate stack of a first MOS device;

    patterning the high-k dielectric layer and the first metal layer to form a second gate stack of a second MOS device; and

    patterning the gate dielectric layer and the silicon layer to form a third gate stack of a third MOS device.

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