Composite gate structure in an integrated circuit
First Claim
1. A method of forming an integrated circuit, the method comprising:
- providing a substrate having a first region and a second region, wherein the first region further comprises a third region and a fourth region;
forming a high-k dielectric layer on the substrate in the first region;
forming a first metal layer having a first work function over the high-k dielectric layer in the fourth region;
forming a second metal layer having a second work function over the high-k dielectric layer in the third region;
forming a gate dielectric layer over the substrate in the second region;
forming a silicon layer directly on the second metal layer and the gate dielectric layer;
patterning the high-k dielectric layer, the second metal layer, and the silicon layer to form a first gate stack of a first MOS device;
patterning the high-k dielectric layer and the first metal layer to form a second gate stack of a second MOS device; and
patterning the gate dielectric layer and the silicon layer to form a third gate stack of a third MOS device.
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Abstract
An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
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Citations
20 Claims
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1. A method of forming an integrated circuit, the method comprising:
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providing a substrate having a first region and a second region, wherein the first region further comprises a third region and a fourth region; forming a high-k dielectric layer on the substrate in the first region; forming a first metal layer having a first work function over the high-k dielectric layer in the fourth region; forming a second metal layer having a second work function over the high-k dielectric layer in the third region; forming a gate dielectric layer over the substrate in the second region; forming a silicon layer directly on the second metal layer and the gate dielectric layer; patterning the high-k dielectric layer, the second metal layer, and the silicon layer to form a first gate stack of a first MOS device; patterning the high-k dielectric layer and the first metal layer to form a second gate stack of a second MOS device; and patterning the gate dielectric layer and the silicon layer to form a third gate stack of a third MOS device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming an integrated circuit, the method comprising:
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providing a substrate having a first region and a second region, wherein the first region further comprises a third region and a fourth region; forming a high-k dielectric layer on the substrate in the first region; forming a first metal layer having a first work function over the high-k dielectric layer in the fourth region; forming a second metal layer having a second work function over the high-k dielectric layer in the third region; forming a third metal layer over the first metal layer in the fourth region, the third metal layer comprising a same material as the second metal layer; forming a gate dielectric layer over the substrate in the second region; forming a silicon layer directly on the second metal layer and the gate dielectric layer; patterning the high-k dielectric layer, the second metal layer, and the silicon layer to form a first gate stack of a first MOS device; patterning the high-k dielectric layer, the first metal layer, and the third metal layer to form a second gate stack of a second MOS device; and patterning the gate dielectric layer and the silicon layer to form a third gate stack of a third MOS device. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of forming an integrated circuit, the method comprising:
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providing a substrate having a first region and a second region, wherein the first region further comprises a third region and a fourth region; forming a high-k dielectric layer on the substrate in the first region; forming a first metal layer having a first work function over the high-k dielectric layer in the fourth region; forming a second metal layer having a second work function over the first metal layer in the fourth region and over the high-k dielectric layer in the third region; forming a gate dielectric layer over the substrate in the second region; forming a silicon layer directly on the second metal layer and the gate dielectric layer; patterning the high-k dielectric layer, the second metal layer, and the silicon layer to form a first gate stack of a first MOS device; patterning the high-k dielectric layer, the first metal layer, and the second metal layer to form a second gate stack of a second MOS device; and patterning the gate dielectric layer and the silicon layer to form a third gate stack of a third MOS device. - View Dependent Claims (17, 18, 19, 20)
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Specification