Method for reduced N+ diffusion in strained Si on SiGe substrate

• US 7,297,601 B2
• Filed: 11/22/2005
• Issued: 11/20/2007
• Est. Priority Date: 09/09/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Dokumaci, Omer H.
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/283,882
• Publication Number:
  US 20060073649A1
• Time in Patent Office: 728 Days
• Field of Search: 438/199, 438/285
• US Class Current: 438/285
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26566 of a cluster, e.g. using a gas cluster ion beam
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming an SiGe layer on a silicon substrate;

relaxing the SiGe layer;

forming an Si cap layer on the SiGe layer;

straining biaxially in tension the Si cap layer to match an underlying relaxed SiGe lattice;

forming a gate electrode;

forming sidewalls on sides of the gate electrode;

forming source and drain extension regions; and

ion implanting an interstitial element into the source and drain extension regions to reduce vacancy concentration in the source and drain extension regions.

2. The method of claim 1, further comprising dividing the substrate into an NMOS region and a PMOS region.

3. The method of claim 1, wherein the interstitial element is Si or O.

4. The method of claim 1, wherein the step of ion-implanting the interstitial element comprises a step of ion-implanting the interstitial element at an implantation concentration of approximately 1×

10¹⁴ atoms/cm² to 1×

10¹⁶ atoms/cm² and at an implantation energy of approximately 0.3 KeV to 100 KeV.

5. The method of claim 4, wherein a concentration peak of the interstitial element and a concentration peak of an N type impurity in the source and drain extension regions are formed at substantially a same depth from an upper surface of the Si cap layer.

6. The method of claim 5, wherein the concentration peak of the interstitial element is formed at a depth of approximately 10 Å

to 20000 Å

from the upper surface of the Si cap layer.

7. The method of claim 1, further comprising a step of annealing.

8. The method of claim 7, wherein the step of annealing is performed at a temperature of approximately 700°

C. to 1200°

C. for approximately 1 second to 3 minutes.

9. The method of claim 1, further comprising a step of forming a gate oxide film between an upper surface of the substrate and the gate electrode.

10. The method of claim 1, further comprising one of:

ensuring that an implant profile of the interstitial element fully contains an N type impurity profile; and

ensuring that a concentration peak of the interstitial element is near an N type impurity peak so as to maximize a diffusion retardation.

11. The method of claim 1, wherein the forming of the source and drain extension regions comprises ion-implantation of an N type impurity in a self-aligned manner.

12. The method of claim 1, wherein the source and drain extension regions are formed by ion-implantation of an N type impurity in a self-aligned manner before low vacancy regions are formed.

13. The method of claim 1, wherein annihilated vacancies are formed by implanting the interstitial element which fully contains an N type impurity profile.

14. The method of claim 1, wherein a concentration peak of the implanted interstitial element is near an N type impurity peak so as to maximize a diffusion retardation.

15. The method of claim 1, further comprising:

using the gate electrode and sidewalls as a mask during implanting of an N type impurity to form the source and drain extension regions.