Method of fabricating and integrating high quality decoupling capacitors

• US 7,297,613 B1
• Filed: 06/09/2005
• Issued: 11/20/2007
• Est. Priority Date: 06/09/2005
• Status: Active Grant

• Current Assignee: National Security Agency
• Original Assignee: The United States of America As Represented By The Director National Security Agency
• Inventors: Mountain, David Jerome
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US11/149,029
• Time in Patent Office: 894 Days
• Field of Search: 438/455, 438/458, 257/E21.122
• US Class Current: 438/458
• CPC Class Codes: H01G 4/01 Form of self-supporting electrodes
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

Method of making an integrated passive, such as a high quality decoupling capacitor, includes providing a first temporary support, a silicon capacitor wafer, and providing an oxide layer and a conductive layer on it. Then, a second temporary support, such as a handle wafer, may be attached to the capacitor wafer (i.e., to the oxide layer on it) by an adhesive bond. The capacitor wafer may then be destructively removed. A second conductive layer is then provided on an exposed backside of the oxide layer. The addition of a second electrode on the second conductive layer yields the desired high quality capacitor. Further processing steps, such as solder bumping, may be carried out while the capacitor wafer is still attached to the handle wafer. When the desired processing steps are complete, the handle wafer is removed, and the relatively thin high quality integrated capacitor wafer results.

Claims

1. Method of making an integrated capacitor, comprising:

a) providing a first temporary support having a topside;

b) providing an oxide layer on the topside of the first temporary support to yield an oxide layer having a topside;

c) providing a first conductive layer on the topside of the oxide layer to yield a first conductive layer having a topside;

d) providing a first electrode on the first conductive layer;

e) providing a second temporary support having a topside;

f) attaching the second temporary support to the topside of the first conductive layer;

g) removing the first temporary support from the oxide layer to expose a backside of the oxide layer;

h) providing a second conductive layer on the exposed backside of the oxide layer to yield a second conductive layer having a backside;

i) providing a second electrode on the backside of the second conductive layer; and

j) the oxide layer, the first and second conductive layers, and the first and second electrodes defining a capacitor.

2. Method as in claim 1, further comprising:

a) adding a solder bump to the backside of the second conductive layer.

3. Method as in claim 1, wherein:

a) the topside of the first conductive layer is attached to the second temporary support with an adhesive.

4. Method as in claim 3, wherein:

a) the adhesive includes an acrylic thinned with acetone to yield a thinned acrylic prior to applying the thinned acrylic to the second temporary support.

5. Method as in claim 3, wherein:

a) the adhesive includes an acrylic thinned with acetone prior to applying the thinned acrylic to the second temporary support and prior to applying the thinned acrylic to the topside of the first conductive layer.

6. Method as in claim 3, wherein:

a) the adhesive includes bisbenzocyclobutene.

7. Method as in claim 1, wherein:

a) the first conductive layer includes an aluminum layer.

8. Method as in claim 1, further comprising:

a) adding a perimeter of solder bumps on the backside of the second conductive layer.

9. Method as in claim 8, further comprising:

a) flip-chip assembling the integrated capacitor to an integrated circuit.

10. Method as in claim 1, wherein:

a) the first temporary support is removed by etching; and

b) the oxide layer is sized and configured to function as an etch stop layer.

11. Method as in claim 1, wherein:

a) the first temporary support includes a silicon wafer;

b) the first conductive layer includes an aluminum layer;

c) the second conductive layer includes an aluminum layer; and

d) the second temporary support includes a handle wafer.

12. Method as in claim 1, wherein:

a) the first temporary support includes a silicon wafer; and

b) the oxide layer includes a thermal oxide grown on the silicon wafer.

13. Method as in claim 12, wherein:

a) the providing of the first conductive layer includes depositing and patterning an aluminum layer on the topside of the thermal oxide layer.

14. Method as in claim 1, wherein:

a) the providing of the first conductive layer includes depositing and patterning an aluminum layer on the topside of the oxide layer.

15. Method as in claim 1, wherein:

a) the first temporary support includes a silicon wafer; and

b) the providing of an oxide layer includes growing a thermal oxide on the silicon wafer.

16. Method as in claim 1, wherein:

a) the second temporary support includes a handle wafer.

17. Method as in claim 16, wherein:

a) the handle wafer includes one of a glass and a stainless handle wafer.

18. Method as in claim 1, wherein:

a) the attaching of the second temporary support to the topside of the first conductive layer includes adhering the topside of the second temporary support to the topside of the first conductive layer with BCB to yield a wafer stack;

b) the first conductive layer includes an aluminum layer; and

c) the wafer stack is treated in a wafer bonder.

19. Method as in claim 1, wherein:

a) the first temporary support includes a capacitor wafer;

b) the oxide layer includes a thermal oxide grown on the capacitor wafer;

c) the first conductive layer includes an aluminum layer;

d) the second conductive layer includes an aluminum layer; and

e) the second temporary support includes a handle wafer having a thickness, and a diameter, the thickness being substantially constant, and the diameter of the handle wafer being substantially the same as a diameter of the capacitor wafer.

20. Method as in claim 19, wherein:

a) the attaching of the handle wafer to the topside of the first aluminum layer includes adhering the topside of the handle wafer to the topside of the first aluminum layer with BCB to yield a wafer stack; and

b) the wafer stack is treated in a wafer bonder.

21. Method as in claim 20, wherein:

a) the treating of the adhered handle wafer and capacitor wafer includes soft baking of the wafer stack in a wafer bonder to preclude the trapping of air in the bond.

22. Method as in claim 1, wherein:

a) the second temporary support is released from the topside of the first conductive layer.

23. Method as in claim 1, further comprising:

a) fabricating additional high quality passive devices, including resistors and inductors.

24. Method as in claim 1, further comprising:

a) directly bonding the integrated capacitor to an integrated circuit.