Semiconductor method and device with mixed orientation substrate

• US 7,298,009 B2
• Filed: 02/01/2005
• Issued: 11/20/2007
• Est. Priority Date: 02/01/2005
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Shum, Danny Pak-Chum, Yan, Jiang, Sung, Chun-Yung, Gutmann, Alois
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US11/047,928
• Publication Number:
  US 20060170045A1
• Time in Patent Office: 1,022 Days
• Field of Search: 257/255, 257347-354, 257/369, 257/371, 257/627, 257/E27.062, 257/E27.112
• US Class Current: 257/357
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.

Claims

1. A semiconductor device comprising:

a semiconductor body having semiconductor material of a first crystal orientation;

a first transistor formed in the semiconductor material of the first crystal orientation;

an insulating layer overlying portions of the semiconductor body;

a semiconductor layer overlying the insulating layer, the semiconductor layer having a second crystal orientation;

a second transistor formed in the semiconductor layer having the second crystal orientation; and

an isolation region disposed over the insulating layer between the first transistor and the second transistor, wherein the isolation region is laterally positioned such that the entire isolation region overlies the insulating layer.

2. The device of claim 1 wherein:

the semiconductor body comprises (100) silicon;

the first transistor comprises an n-channel field effect transistor;

the semiconductor layer comprises (110) silicon; and

the second transistor comprises a p-channel field effect transistor.

3. The device of claim 1, wherein the isolation region has a lateral dimension that is as small as a minimum lithographic dimension of the device.

4. The device of claim 1 wherein the first transistor is formed in an epitaxially grown portion of the semiconductor body and wherein the second transistor is formed in an epitaxially grown portion of the semiconductor layer.

5. The device of claim 4 wherein a portion of the isolation region overlies a portion of the semiconductor layer.

7. The device of claim 1 wherein:

the semiconductor body comprises (100) silicon;

the first transistor comprises an n-channel field effect transistor;

the semiconductor layer comprises (110) silicon; and

the second transistor comprises a p-channel field effect transistor.

8. The device of claim 1, wherein the semiconductor region comprises an epitaxially grown semiconductor region.

9. The device of claim 1, wherein the isolation region has a lateral dimension that is as small as a minimum lithographic dimension of the device.

6. A semiconductor device comprising:

a semiconductor body having semiconductor material of a first crystal orientation;

a first transistor formed in the semiconductor material of the first crystal orientation;

an insulating layer overlying portions of the semiconductor body;

a semiconductor layer overlying the insulating layer, the semiconductor layer having the second crystal orientation;

a semiconductor region overlying the semiconductor layer, the semiconductor region having the second crystal orientation;

a second transistor formed in the semiconductor region; and

an isolation region disposed over the semiconductor body and located laterally between the first transistor and the second transistor;

wherein the semiconductor region has a lateral dimension that is less than a lateral dimension of the semiconductor layer so that a portion of the semiconductor layer extends beyond the semiconductor region, wherein the isolation region overlies the portion of the semiconductor layer that extends beyond the semiconductor region.

10. The device of claim 6 wherein the semiconductor body comprises a bulk monocrystalline silicon substrate.

11. The device of claim 10 wherein the silicon substrate comprises (100) silicon and wherein the semiconductor layer comprises (110) silicon.

12. A semiconductor device comprising:

a semiconductor body having semiconductor material of a first crystal orientation;

an insulating layer overlying portions of the semiconductor body;

a semiconductor layer overlying the insulating layer, the semiconductor layer having a second crystal orientation, the semiconductor layer having an opening over a portion of the semiconductor body, the opening being defined by sidewalls in the semiconductor layer;

a first semiconductor region overlying the semiconductor body and having an upper surface, the first semiconductor region being of the first crystal orientation;

a second semiconductor region overlying the semiconductor layer and having an upper surface that is substantially co-planar with the upper surface of the first region, the second semiconductor region being of the second crystal orientation, wherein the second semiconductor region has a lateral dimension that is less than a lateral dimension of the semiconductor layer so that a portion of the semiconductor layer extends beyond the semiconductor region;

an isolation region disposed over the semiconductor body and located laterally between the first region and the second region, the isolation region having sidewalls that are substantially aligned with the sidewalls of the insulating layer such that the first semiconductor region abuts the substantially aligned sidewalls, wherein the isolation region overlies the portion of the semiconductor layer that extends beyond the second semiconductor region;

a first transistor formed in the first semiconductor region; and

a second transistor formed in the second semiconductor region.

13. The device of claim 12, wherein the second semiconductor region comprises an epitaxially grown semiconductor region.

14. The device of claim 12 wherein:

the semiconductor body comprises (100) silicon;

the first transistor comprises an n-channel field effect transistor;

the semiconductor layer comprises (110) silicon; and

the second transistor comprises a p-channel field effect transistor.

15. The device of claim 12, wherein the first semiconductor region comprises an epitaxially grown semiconductor region.

16. The device of claim 15, wherein the second semiconductor region comprises an epitaxially grown semiconductor region.

17. The device of claim 12 wherein the semiconductor body comprises a bulk monocrystalline silicon substrate.

18. The device of claim 17 wherein the silicon substrate comprises (100) silicon and wherein the semiconductor layer comprises (110) silicon.