Radiation-hardened transistor and integrated circuit

• US 7,298,010 B1
• Filed: 02/21/2006
• Issued: 11/20/2007
• Est. Priority Date: 02/21/2006
• Status: Active Grant

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Ma, Kwok K.
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Valentine; Jami M
• Application Number:
  US11/358,391
• Time in Patent Office: 637 Days
• Field of Search: 257/369, 257/347, 257/349, 257/358, 257/357, 257/371, 257/401, 257/414, 257/500, 438/197, 438/332, 327/112, 327/537, 327/108, 326/83
• US Class Current: 257/359
• CPC Class Codes: H01L 23/556 against alpha rays
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits

Abstract

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Claims

1. A composite transistor for use in radiation hardening a complementary metal-oxide semiconductor (CMOS) integrated circuit, comprising:

a circuit transistor of an n-type or p-type having a source terminal, a drain terminal, a gate terminal and a body terminal; and

a blocking transistor of the same n-type or p-type having a source terminal, a drain terminal, a gate terminal and a body terminal, with the gate terminals of the circuit and blocking transistors being connected together to form a gate terminal for the composite transistor, with the source terminal of the circuit transistor forming a source terminal for the composite transistor, with the drain terminal of the blocking transistor forming a drain terminal for the composite transistor, with the source terminal of the blocking transistor being connected to the drain terminal of the circuit transistor, with the body terminal of the circuit transistor forming a body terminal for the composite transistor, and with the body terminal of the blocking transistor being connected to the source terminal of the blocking transistor and with the body terminal of the blocking transistor being electrically isolated from any other connection point in the CMOS integrated circuit.

2. The composite transistor of claim 1 further comprising a silicon-on-insulator (SOI) substrate wherein the circuit and blocking transistors are formed, with the SOI substrate having a buried oxide layer sandwiched between a monocrystalline silicon body and a monocrystalline silicon layer, and with the circuit transistor and the blocking transistor being formed within a common island defined within the monocrystalline silicon layer with the island being surrounded by a field oxide for electrical isolation, and with a body of the circuit transistor being separated and electrically isolated from a body of the blocking transistor by a common drain/source region which forms a drain for the circuit transistor and a source for the blocking transistor.

3. The composite transistor of claim 1 further comprising a silicon-on-insulator (SOI) substrate wherein the circuit and blocking transistors are formed, with the SOI substrate having a buried oxide layer sandwiched between a monocrystalline silicon body and a monocrystalline silicon layer, with the circuit transistor and the blocking transistor being formed in separate islands defined within the monocrystalline silicon layer, with each island being surrounded by a field oxide for electrical isolation.

4. The composite transistor of claim 1 further comprising a bulk semiconductor substrate wherein the circuit transistor and the blocking transistor are formed.

5. The composite transistor of claim 4 wherein the bulk semiconductor substrate comprises silicon.

6. The composite transistor of claim 4 wherein the bulk semiconductor substrate comprises a p-type-doped substrate having a separate n-type-doped well wherein each p-type composite transistor is formed, and further having a separate p-type-doped well wherein each n-type composite transistor is formed, with each p-type doped well being located within another n-type-doped well to electrically isolate each p-type-doped well from the p-type-doped substrate.

7. The composite transistor of claim 4 wherein the bulk semiconductor substrate comprises an n-type-doped substrate having a separate p-type-doped well wherein each n-type composite transistor is formed, and further having a separate n-type-doped well wherein each p-type composite transistor is formed, with each n-type-doped well being located within another p-type-doped well to electrically isolate each n-type-doped well from the n-type-doped substrate.

8. A radiation-hardened CMOS integrated circuit, comprising:

a semiconductor substrate; and

a plurality of interconnected n-type and p-type composite transistors formed on the semiconductor substrate, with each n-type and p-type composite transistor further comprising a circuit transistor and a blocking transistor of the same n-type or p-type, with the circuit and blocking transistor each having a source terminal, a drain terminal, a gate terminal, and a body terminal, and with the gate terminals of the circuit and blocking transistors being connected together to form a gate terminal for the composite transistor, with the source terminal of the circuit transistor forming a source terminal for the composite transistor, with the drain terminal of the blocking transistor forming a drain terminal for the composite transistor, with the source terminal of the blocking transistor being connected to the drain terminal of the circuit transistor, with the body terminal of the circuit transistor forming a body terminal for the composite transistor, and with the body terminal of the blocking transistor being connected to the source terminal of the blocking transistor and with the body terminal of the blocking transistor being electrically isolated from any other connection point in the CMOS integrated circuit.

9. The radiation-hardened CMOS integrated circuit of claim 8 wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

10. A radiation-hardened CMOS integrated circuit comprising:

a bulk silicon substrate; and

a plurality of interconnected n-type and n-type composite transistors formed on the bulk silicon substrate, with each n-type and p-type composite transistor further comprising a circuit transistor and a blocking transistor of the same n-type or n-type, with the circuit and blocking transistor each having a source terminal, a drain terminal, a gate terminal, and a body terminal, and with the gate terminals of the circuit and blocking transistors being connected together to form a gate terminal for the composite transistor, with the source terminal of the circuit transistor forming a source terminal for the composite transistor, with the drain terminal of the blocking transistor forming a drain terminal for the composite transistor, with the source terminal of the blocking transistor being connected to the drain terminal of the circuit transistor with the body terminal of the circuit transistor forming a body terminal for the composite transistor, and with the body terminal of the blocking transistor being connected to the source terminal of the blocking transistor and with the body terminal of the blocking transistor being electrically isolated from any other connection point in the CMOS integrated circuit and with a body of each blocking transistor forming a part of a reverse-biased semiconductor p-n junction to electrically isolate the body of that blocking transistor from the bulk silicon substrate, and from every other circuit transistor and blocking transistor in the radiation-hardened CMOS integrated circuit.

11. A radiation-hardened CMOS integrated circuit, comprising:

a first p-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the body terminal of the first p-channel transistor being connected to the source terminal thereof;

a second p-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the gate terminal of the second p-channel transistor being connected to the gate terminal of the first p-channel transistor, and with the source and body terminals of the second p-channel transistor being connected together and further being connected only to the drain terminal of the first p-channel transistor and to no other node in the radiation-hardened CMOS integrated circuit;

a third n-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the body terminal of the third n-channel transistor being connected to the source terminal thereof; and

a fourth n-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the gate terminal of the fourth n-channel transistor being connected to the gate terminal of the third n-channel transistor, and with the source and body terminals of the fourth n-channel transistor being connected together and further being connected only to the drain terminal of the third n-channel transistor and to no other node in the radiation-hardened CMOS integrated circuit.

12. The radiation-hardened CMOS integrated circuit of claim 11 wherein the source terminal of the first p-channel transistor is connected to a first reference potential, and the source terminal of the third n-channel transistor is connected to a second reference potential, and the gates of the first and second p-channel transistors are connected to the gates of the third and fourth n-channel transistors to provide an input connection for the radiation-hardened CMOS integrated circuit, and the drain terminals of the second p-channel transistor and the fourth n-channel transistor are connected together to provide an output connection for the radiation-hardened CMOS integrated circuit.

13. A radiation-hardened CMOS integrated circuit comprising:

a first p-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the body terminal of the first p-channel transistor being connected to the source terminal thereof;

a second p-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the gate terminal of the second p-channel transistor being connected to the gate terminal of the first p-channel transistor, and with the source and body terminals of the second p-channel transistor being connected together and further being connected only to the drain terminal of the first p-channel transistor and to no other node in the radiation-hardened CMOS integrated circuit;

a third n-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the body terminal of the third n-channel transistor being connected to the source terminal thereof; and

a fourth n-channel transistor having a source terminal, a drain terminal, a gate terminal and a body terminal, with the gate terminal of the fourth n-channel transistor being connected to the gate terminal of the third n-channel transistor, and with the source and body terminals of the fourth n-channel transistor being connected together and further being connected only to the drain terminal of the third n-channel transistor and to no other node in the radiation-hardened CMOS integrated circuit

wherein the source terminal of the first p-channel transistor is connected to the source terminal of the third n-channel transistor to provide an input connection for the radiation-hardened CMOS integrated circuit, and the drain terminal of the second p-channel transistor is connected to the drain terminal of the fourth n-channel transistor to provide an output connection for the radiation-hardened CMOS integrated circuit.

14. A radiation-hardened CMOS integrated circuit, comprising:

a semiconductor substrate,

a plurality of interconnected n-type and p-type metal-oxide semiconductor (MOS) transistors on the semiconductor substrate, with every n-type and p-type MOS transistor in the radiation-hardened CMOS integrated circuit being a composite transistor which further comprises;

a circuit transistor of an n-type or p-type having a source terminal, a drain terminal, a gate terminal, and an unconnected or omitted body terminal; and

a blocking transistor of the same n-type or p-type having a source terminal, a drain terminal a gate terminal, and an unconnected or omitted body terminal with the gate terminals of the circuit and blocking transistors being connected together to form a gate terminal for the composite transistor, with the source terminal of the circuit transistor forming a source terminal for the composite transistor, with the drain terminal of the blocking transistor forming a drain terminal for the composite transistor, and with the source terminal of the blocking transistor being connected to the drain terminal of the circuit transistor.

15. The radiation-hardened CMOS integrated circuit of claim 14 wherein the substrate comprises a silicon-on-insulator (SOI) substrate.