Active device array substrate, liquid crystal display panel and examining methods thereof

• US 7,298,165 B2
• Filed: 01/20/2006
• Issued: 11/20/2007
• Est. Priority Date: 01/20/2006
• Status: Expired due to Fees

• Current Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Original Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Inventors: Chang, Yuan-Hao, Huang, Chin-Hai, Lin, Kuang-Hsiang
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US11/307,044
• Publication Number:
  US 20070170948A1
• Time in Patent Office: 669 Days
• Field of Search: None
• US Class Current: 324/760.02
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136254 Checking; Testing

Abstract

Pixel units are disposed in a display region of a substrate, and scan lines and data lines are used to control the pixel units. Inner short ring includes a first segment, a second segment and a connecting segment connecting both segments. The gates and sources of the first and second active device connect with the first and second segments respectively, and the drains connect with the connecting segment. The gates and sources of part of the third active devices connect with the first segment, and the drains connect with the odd scan lines. The gates and sources of other third active devices connect with the second segment, and the drains connect with the even scan lines. The gates of the fourth active devices connect with connecting lines, and the sources connect with data testing lines, and the drains connect with the odd and even data lines respectively.

Claims

1. An active device array substrate, comprising:

a substrate, having a display region and a peripheral circuit region;

a plurality of pixel units, disposed in the display region;

a plurality of scan lines, disposed on the substrate;

a plurality of data lines, disposed on the substrate, wherein the scan lines and data lines control the pixel units;

two data testing lines, disposed in the peripheral circuit region;

an inner short ring, disposed in the peripheral circuit region, wherein the inner short ring comprises a first segment, a second segment and a connecting segment electrically connecting between the first segment and the second segment;

a first active device, having a gate, a source and a drain, wherein the gate and the source connect with the first segment, and the drain connects with the connecting segment;

a second active device, having a gate, a source and a drain, wherein the gate and the source connect with the second segment, and the drain connects with the connecting segment;

a plurality of third active devices, disposed in the peripheral circuit region, each of the third active devices having a gate, a source and a drain, wherein the gates and the sources of part of the third active devices connect with the first segment, and the corresponding drains connect with the odd scan lines, while the gates and the sources of other third active devices connect with the second segment, and the corresponding drains connect with the even scan lines; and

a plurality of fourth active devices, disposed in the peripheral circuit region, each of the fourth active devices having a gate, a source and a drain, wherein the gates of the fourth active devices connect with the connecting segment, part of the sources connect with one of the data testing lines respectively, and the corresponding drains connect with the odd data lines, while the other sources connect with the other one of the data testing lines respectively, and the corresponding drains connect with the even data lines.

2. The active device array substrate as claimed in claim 1, wherein the inner short ring is located outside the data testing lines.

3. The active device array substrate as claimed in claim 1, wherein each of the pixel units comprises:

a fifth active device, electrically connected with the corresponding scan line data line; and

a pixel electrode, electrically connected with the third active device.

4. The active device array substrate as claimed in claim 1, further comprising a plurality of examining pads disposed in the peripheral circuit region on the substrate, wherein the first segment of the inner short ring and the terminal of the second segment connect with one of the examining pads respectively, and one terminal of each data testing line connects with one of the examining pads respectively.

5. The active device array substrate as claimed in claim 1, further comprising a plurality of common lines and an examining line connecting one terminal of the common lines, wherein the common lines are disposed on the substrate, and extend from the display region to the peripheral circuit region, while the examining line is disposed in the peripheral circuit region on the substrate.

6. The active device array substrate as claimed in claim 1, wherein the data testing lines are dummy data lines, and the data testing lines are located at two sides of the data lines.

7. The active device array substrate as claimed in claim 1, wherein the data testing lines are another inner short ring.

15. A method for examining the active device array substrate, suitable for the active device array substrate as claimed in claim 1, the method comprising:

inputting a first scan signal to the first segment of the inner short ring to start the first active device and the fourth active devices, the first scan signal being input to the odd scan lines by the third active devices;

inputting a second scan signal to the second segment of the inner short ring to shut down the second active device and part of the third active devices connected with the even scan lines, wherein the first scan signal is a Vgh signal, and the second scan signal is a Vgl signal;

inputting a first data signal to one of the data testing lines, the first data signal being input to the corresponding data lines by part of the fourth active devices; and

measuring the voltage of the other data testing line.

16. A method for examining the active device array substrate, suitable for the active device array substrate as claimed in claim 1, the method comprising:

inputting a first scan signal to the first segment of the inner short ring;

inputting a second scan signal to the second segment of the inner short ring; and

measuring the voltage of the data testing lines.

17. The method for examining the active device array substrate as claimed in claim 16, wherein the first scan signal is a Vgh signal, and the second scan signal is a Vgl signal.

18. The method for examining the active device array substrate as claimed in claim 16, wherein the first and second scan signals are Vgh signals.

19. A method for examining the active device array substrate, suitable for the active device array substrate as claimed in claim 5, the method comprising:

inputting a first scan signal to the first segment of the inner short ring;

inputting a second scan signal to the second segment of the inner short ring; and

measuring the voltage of the examining line.

20. The method for examining the active device array substrate as claimed in claim 19, wherein the first scan signal is a Vgh signal, and the second scan signal is a Vgl signal.

21. The method for examining the active device array substrate as claimed in claim 19, wherein the first and second scan signals are Vgh signals.

22. A method for examining the active device array substrate, suitable for the active device array substrate as claimed in claim 5, the method comprising:

inputting a first scan signal to the first segment of the inner short ring;

inputting a second scan signal to the second segment of the inner short ring, wherein at least one of the first and second scan signals is a Vgh signal;

inputting a first data signal to one of the data testing lines, the first data signal being input to the corresponding data lines by part of the fourth active devices; and

measuring the voltage of the examining line.

8. An liquid crystal display panel, comprising:

an active device array substrate, including;

a substrate, having an adjacent display region and a peripheral circuit region;

a plurality of pixel units, disposed in the display region;

a plurality of scan lines, disposed on the substrate;

a plurality of data lines, disposed on the substrate, wherein the scan lines and the data lines control the pixel units;

two data testing lines, disposed in the peripheral circuit region;

an inner short ring, disposed in the peripheral circuit region, wherein the inner short ring includes a first segment, a second segment and a connecting segment electrically connected between the first segment and the second segment;

a first active device, having a gate, a source and a drain, wherein the gate and the source connect with the first segment, and the drain connects with the connecting segment;

a second active device, having a gate, a source and a drain, wherein the gate and the source connect with the second segment, and the drain connects with the connecting segment;

a plurality of third active devices, disposed in the peripheral circuit region, each of the third active devices having a gate, a source and a drain, wherein the gates and the sources of part of the third active devices connect with the first segment, and the corresponding drains connect with the odd scan lines, while the gates and the sources of other third active devices connect with the second segment, and the corresponding drains connect with the even scan lines;

a plurality of fourth active devices, disposed in the peripheral circuit region, each of the fourth active devices having a gate, a source and a drain, wherein the gates of the fourth active devices connect with the connecting segment, part of the sources connect with one of the data testing lines respectively, and the corresponding drains connect with the odd data lines, while the other the sources connect with the other one of the data testing lines, and the corresponding drains connect with the even data lines;

a color filter substrate; and

a liquid crystal layer, disposed between the color filter substrate and the active device array substrate.

9. The liquid crystal display panel as claimed in claim 8, wherein the inner short ring of the active device array substrate is located outside the data testing lines.

10. The liquid crystal display panel as claimed in claim 8, wherein each of the pixel units of the active device array substrate comprises:

a fifth active device, electrically connected with the corresponding scan line and data line; and

a pixel electrode, electrically connected with the third active device.

11. The liquid crystal display panel as claimed in claim 8, wherein the active device array substrate further comprises a plurality of examining pads disposed in the peripheral circuit region on the substrate, and the terminals of the first segment and the second segment of the inner short ring connect with one of the examining pads respectively, and one terminal of each data testing line connects with one of the examining pads.

12. The liquid crystal display panel as claimed in claim 8, wherein the active device array substrate further comprises a plurality of common lines and a examining line connected with one terminal of the common lines, wherein the common lines are disposed on the substrate, and extend from the display region to the peripheral circuit region, while the examining line is disposed in the peripheral circuit region on the substrate.

13. The liquid crystal display panel as claimed in claim 8, wherein the data testing lines of the active device array substrate are dummy data lines, and the data testing lines are located at two sides of the data lines.

14. The liquid crystal display panel as claimed in claim 8, wherein the data testing lines of the active device array substrate are another inner short ring.

23. A method for examining the liquid crystal display panel, suitable for the liquid crystal display panel as claimed in claim 8, the examining method comprising:

providing a light source, and disposing the liquid crystal display panel above the light source;

inputting a first scan signal to the first segment of the inner short ring;

inputting a second scan signal to the second segment of the inner short ring;

inputting a first data signal to one of the data testing lines; and

inputting a second data signal to the other data testing line.

24. The examining method as claimed in claim 23, wherein after inputting the first and second scan signals and the first and second data signals to the first segment, the second segment, one of the data testing lines and the other data testing line, the liquid crystal display panel displays a black, white or gray image.

25. The examining method as claimed in claim 23, wherein after inputting the first and second scan signals and the first and second data signals to the first segment, the second segment, one of the data testing lines and the other data testing line, the liquid crystal display panel displays an image of bright horizontal or vertical line.

26. The examining method as claimed in claim 23, wherein after inputting the first and second scan signals and the first and second data signals to the first segment, the second segment, one of the data testing lines and the other data testing line, the liquid crystal display panel displays an image of bright dot array.